Stmicroelectronics S.r.l.

Stmicroelectronics Gmbh

Marco Bisio

Marco Pasotti

Pier Luigi Rolandi

Alessandro Rocchi

Guido De Sandre

Roberto Guerrieri

Marco Tartagni

Giovanni Guaitini

A digital device for testing and calibrating the oscillation frequency of an integrated oscillator circuit, the testing and calibrating device has as input at least first and second control parameters corresponding to limiting values of a predetermined range of values of the oscillation frequency sought for the integrated oscillator circuit, and it includes a comparison circuit for comparing a signal of known duration and a signal from the integrated oscillator circuit; a circuit connected to the comparison circuit, for generating calibration values for the signal from the integrated oscillator circuit; and a circuit for forcing storage of final calibration values of the signal from the integrated oscillator circuit into a storage and control section of the integrated oscillator circuit.

Device for testing and calibrating the oscillation frequency of an integrated oscillator

A FLASH memory is organized in a plurality of physical sectors which may be split into a plurality of singularly addressable logic sectors. Each logic sector may include a memory space of a predetermined size and a chain pointer assuming a neutral value or a value pointing to a second logic sector associated with a respective chain pointer at the neutral value. Each logic sector may also include a status indicator assuming at least one of a first value if the logic sector is empty, a second value if the data therein belongs to the logic sector, a third value if the data does not belong to the logic sector, and a fourth value if the data has been erased. Further, each logic sector may include a remap pointer assuming the neutral value or a value pointing directly or indirectly to the chain pointer of a third logic sector.

Logic partitioning of a nonvolatile memory array

A circuit technique to reduce the input capacitance line of a charge integrator is described. This approach is particularly tailored for embedded read-out circuits in solid-state integrated sensors. An integrated charge amplifier described herein includes a generic amplifier element and a high speed buffer which drives a metal shield placed underneath the input line. The metal shield therefore follows the potential of the input line and thereby reduces the capacitance between the input line and ground.

Parasitic capacitance reduction for passive charge read-out

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Modena, Italy

Marco Bisio