Stmicroelectronics International N.v.

Stmicroelectronics (Rousset) Sas

Stmicroelectronics N.v.

Stmicroelectronics Design and Application Gmbh

Stmicroelectronics Gmbh

Stmicroelectronics (Grenoble 2) Sas

Marco Bildgen

Francesco La Rosa

Jean Devin

Juergen Boehler

An integrated circuit comprises a memory device including a memory plane having non-volatile memory cells and being non-observable in read mode from outside the memory device, a controller, internal to the memory device, configured to detect the memorized content of the memory plane, and when the memorized content contains locking content, automatically lock any access to the memory plane from outside the memory device, the integrated circuit then being in a locked status, and authorize delivery outside the memory device of at least one sensitive datum stored in the memory plane.

Protection of an integrated circuit

In an embodiment an integrated device includes a first physical unclonable function module configured to generate an initial data group and management module configured to generate an output data group from at least the initial data group, authorize only D successive deliveries of the output data group on a first output interface of the device, D being a non-zero positive integer, and prevent any new generation of the output data group.

Physically unclonable function device

In an embodiment a non-volatile memory device includes a memory plane including at least one memory area including an array of memory cells having two rows and N columns, wherein each memory cell comprises a state transistor having a control gate and a floating gate selectable by a vertical selection transistor buried in a substrate and including a buried selection gate, and wherein each column of memory cells includes a pair of twin memory cells, two selection transistors of the pair of twin memory cells having a common selection gate and a processing device configured to store in the memory area information including a succession of N bits so that, with exception of the last bit of the succession, a current bit of the succession is stored in two memory cells located on the same row and on two adjacent columns and a current bit and the following bit are respectively stored in two twin cells.

Non-volatile memory device readable only a predetermined number of times

A method may be for detecting potentially suspicious operation of an electronic device configured to operate in the course of activity sessions. The method may include within the device, a metering, from an initial instant of the number of activity sessions having a duration below a first threshold, and a comparison of this number with a second threshold.

Method for detecting potentially suspicious operation of an electronic device and corresponding electronic device

A method for writing and reading data in a main nonvolatile memory having target pages in which data are to be written and read, the method including providing a nonvolatile buffer having an erased area, providing a volatile cache memory, and receiving a write command to update a target page with updating data the length of which can be lower than the length of a page. The method also includes, in response to the write command, writing the updating data into the erased area of the nonvolatile buffer, together with management data of a first type, and recording an updated version of the target page in the cache memory or updating in the cache memory a previously updated version of the target page.

Growing community of inventors

Habere-Poche, France

Marco Bildgen