Nxp B.v.

Goodix Technology (hk) Company Limited

Marco Berkhout

Benno Krabbenborg

Paulus Petrus Franciscus Maria Bruin

Massimo Ciacci

Henricus Cornelis Johannes Buthker

Johannes Petrus Maria Van Lammeren

Martin Kessel

Han Martijn Schuurmans

Fred Mostert

Mattheus Johan Koerts

Johannes Van Zwol

Peter Van De Haar

Lutsen Ludgerus Albertus Hendrikus Dooper

Johan Somberg

Maarten Van Dommelen

Armand Stuivenwold

Wilfred Repko

Quino Sandifort

Lûtsen Ludgerus Albertus Hendrikus Dooper

Jokin Segundo Babarro

Lutsen Ludgerus Albertus Hendrikus

Bernardus Henricus Krabbenborg

Lutsen Dooper

Gayatri Agarwal

Chen Chen

Maarten Wilhelmus Henricus Marie Van Dommelen

A sense amplifier circuit comprising a first-, second-, third- and fourth-amplification-blocks, each amplification-block comprising: an amplification-block-transistor comprising and an amplification-block-resistor. The amplification-block-transistor includes: a first-conduction-channel-terminal, a second-conduction-channel-terminal that is connected to an amplification-block-output-node, and a control-terminal that is connected to an amplification-block-control-node. The sense amplifier circuit also comprises: an amplification-block-resistor connected in series between an amplification-block-input-node and the first-conduction-channel-terminal; a first-bias-voltage-source connected to the amplification-block-control-nodes of the first- and third-amplification-blocks, a second-bias-voltage-source connected to the amplification-block-control-nodes of the second- and fourth-amplification-blocks. The sense amplifier circuit also comprises: a first-common-mode-voltage-resistor connected in series between a first-sensed-output-terminal and a common-mode-voltage-node; and a second-common-mode-voltage-resistor connected in series between a second-sensed-output-terminal and the common-mode-voltage-node.

Sense amplifier circuit

A circuit comprising: an input terminal configured to receive an input-signal; an output terminal configured to provide an output-signal; a reference circuit comprising: a first output terminal configured to provide a first-reference-signal; a second output terminal configured to provide a second-reference-signal; and a third output terminal configured to provide a third-reference-signal. A comparator-block configured to compare a comparator-input-voltage-signal representative of signalling received at the input terminal with: (i) the first-reference-signal, (ii) the second-reference-signal and (iii) the third-reference-signal in order to generate a comparison-signal. A control-block configured to set the output-signal as one of at least two voltage levels based on the comparison-signal; and an input-control-circuit configured to apply a feedback-control-signal to the input-terminal based on the comparison-signal.

Circuit for generating a plurality of reference voltages for controlling feedback within the circuit

A loop-filter comprising: a first-integrator, and one or more further-integrators. The first-integrator is an active-RC integrator, and comprises a first-integrator-input-terminal configured to receive: (i) an input-signal, and (ii) a feedback-signal; a first-integrator-first-output-terminal configured to provide a first-integrator-first-output-signal; and one or more first-integrator-further-output-terminals. Each of the one or more further-integrators is a Gm-C integrator, and they are connected in series between the first-integrator-first-output-terminal and a loop-filter-output-terminal. For a first further-integrator in the series, the further-integrator-input-terminal is configured to receive the first-integrator-first-output-signal. For any subsequent further-integrators in the series, the further-integrator-input-terminal is configured to receive: (i) the further-integrator-output-signal from the preceding further-integrator in the series; and (ii) one of the first-integrator-further-output-signals.

Amplifier circuit

An amplifier circuit comprising: a delta-PWM-modulator, a three-level-DAC, a loop-integrator, and a comparator. The delta-PWM-modulator receives a digital-input-signal; and processes the digital-input-signal and a modulator-triangular-signal to generate a delta-pulse-width-modulation-signal. The delta-pulse-width-modulation-signal is representative of the difference between a square-wave-carrier-signal and a digital-pulse-width-modulation of the digital-input-signal. The three-level-DAC receives the delta-pulse-width-modulation-signal from the delta-PWM-modulator and provides a three-level-analog-signal. The loop-integrator comprises: a virtual-ground-node-terminal configured to receive: (i) the three-level-analog-signal from the three-level DAC; and (ii) a feedback-signal from an output stage of the amplifier circuit via a feedback loop; and an integrator-output-terminal configured to provide a loop-integrator-output-signal. The comparator comprises a comparator-input-terminal configured to receive the loop-integrator-output-signal; a comparator-reference-terminal configured to receive a triangular-reference-signal that corresponds to the integral of the square-wave-carrier-signal; and a comparator-output-terminal configured to provide a drive-signal suitable for driving an output-stage of the amplifier circuit.

Aspects are directed to an amplifier circuit including a signal processing circuit and a calibration circuit. In certain specific embodiments, the signal processing circuit includes a signal combiner and a closed-loop feedback path, and the signal processing circuit is designed to provide a loop transfer function for a derived signal partly representing contributions from an audio input signal, a control or pilot signal having a target frequency range, and a calibration signal. The signal combiner is designed to combine aspects of the control or pilot signal and aspects of the audio input signal, and the calibration circuit is designed to adjust an effective gain of the derived signal in response to whether a unity-gain frequency of a signal in the closed-loop feedback path, as provided via the loop transfer function, is higher or lower than the target frequency range. Consistent therewith and in yet more specific embodiments, such an amplifier circuit can define the target frequency range relative to the transfer function and an associated unity-gain frequency.

Automatic loop gain calibration in amplification circuits

A wireless electrical power receiver for inductively generating alternating current power in a wireless electrical power transfer system having a transmission resonant frequency, the receiver comprising a receiver resonator having a receiver resonant frequency, the receiver resonator constructed and arranged such that the receiver resonant frequency is detuned from the transmission resonant frequency.

Wireless power receiver

An audio amplifier system is described comprising: a variable gain audio processor for processing digital audio signal, a digital to analog converter coupled to the audio processor, and configured to receive the processed digital audio signal, a variable gain amplifier having an input coupled to the output of the digital to analog converter and operably connected to a power supply, a controller coupled to the variable gain audio processor and the variable gain amplifier and configured to switch the audio amplifier system between a first operating mode having a first power supply voltage value and a second operating mode having a second higher power supply voltage value; wherein the controller is operable in the first operating mode to set the audio amplifier system gain to a desired gain value and in the second operating mode to maintain the desired gain value.

Audio amplifier system

A speaker driver comprising an amplifier, configured to receive a test signal that comprises a plurality of equivalent test-blocks, and provide measurement-signalling for a speaker at the amplifier output. The measurement-signalling comprising a plurality of measurement-blocks, wherein each of the measurement-blocks corresponds to the output of the amplifier for one of the plurality of test-blocks. The speaker driver also includes an output-current-sensor configured to: measure a current level of the measurement-signalling, and provide sensed-signalling that comprises a plurality of sensed-blocks, wherein each of the plurality of sensed-blocks corresponds to one of the plurality of measurement-blocks of the measurement-signalling. The speaker driver further includes a processor configured to either: (a) combine the plurality of sensed-blocks to provide a time-averaged-block; and determine a frequency-spectrum of the time-averaged-block; or (b) determine a frequency-spectrum of each of the plurality of sensed-blocks to provide a plurality of frequency-spectrum-sensed-blocks; and combine the plurality of frequency-spectrum-sensed-blocks to provide a time-averaged-frequency-spectrum-block.

Speaker driver

In High Voltage CMOS technologies the supply voltage is typically higher than the maximum allowed gate voltage. In a switching output stage of amplifiers such class-D amplifiers and DC-DC converters the gates of the power field effect transistors need to be charged quickly. This requires a gate driver that is capable of delivering large currents without exceeding the maximum allowed voltage on the gate of the power field effect transistors.

Gate driver circuit

An amplifier system is described. The amplifier system may amplify an audio signal transmitted via a connected loudspeaker in a first mode of operation. In a second mode of operation the amplifier system may amplify a signal generated by the loudspeaker operated in reverse as a microphone. Because a loudspeaker is less sensitive than a microphone the amplifier system may be used to acquire audio at high sound pressure levels for example at a concert or while making a phone-call in a noisy environment for example with a high level of wind noise.

Amplifier system

A Class D power amplifier is for driving a load between first and second output nodes defined between two bridges. A controller is adapted to derive an amplifier hold signal when an overcurrent state is detected in an output bridge, and to prevent switching of the other output bridge between the two main output states.

Class D amplifier and control method

A method of operating a switched-mode power supply (SMPS) for supplying power to a load circuit, which draws a supply current that varies with an input signal to the load circuit is disclosed. The method comprises monitoring the input signal and controlling the amount of accumulated energy transferred for consumption by the load circuit, in use, in accordance with the input signal.

Switched-mode power supply and method of operation

A switchable current source in which a reference voltage value to be used in driving the gate of an output transistor is sampled and stored. The reference voltage is derived using a reference current source which feeds a current sensing transistor. The current sensing transistor is turned off when the output transistor is turned off, so that the reference current source then does not consume power. A large reference current Iref can then be used for a short time.

Switchable current source circuit and method

Disclosed is a class D amplifier comprising a modulation stage having a first input for receiving an input signal and an output for producing a modulated version of the input signal; a plurality of power stages, each power stage being responsive to said modulation stage and comprising a first switch and a second switch coupled in series between a first voltage source and a second voltage source, each power stage comprising an output node between the first switch and the second switch; and a power stage control circuit for measuring the input signal level and enabling a selected number of the power stages as a function of the measured input signal level. A method for controlling such a class D amplifier is also disclosed.

Amplifier and amplifier control method

A method and circuit for providing a switched current source output has a precharge mode, in which a charge storage device is charged to a reference voltage, and the gate of an output transistor is discharged. In a discharge mode, the charge storage device is discharged to the gate of the output transistor to raise the gate voltage by an amount depending on the charge flow.

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Tiel, Netherlands

Marco Berkhout