Stmicroelectronics S.r.l.

Stmicroelectronics International N.v.

Marco Attanasio

Alberto Cattani

Stefano Ramorini

Giuseppe Calderoni

Giovanni Bellotti

Marco Pinsero

A load is powered between positive and negative rails. A switching converter generates the negative rail voltage based on an input voltage, with a power transistor involved therein. A replica generator produces a replica voltage mirroring the drain-to-source voltage of the power transistor. A buffer buffers the replica voltage. A first switch selectively connects the buffered voltage to an output node, in response to a control signal with a duty-cycle proportional to the input voltage divided by the negative rail voltage. A second switch selectively connects the buffered voltage to ground, according to the inverse of the control signal, resulting in a PWM signal at the output node. An output filter filters the PWM signal to generate a sense voltage indicative of the output current flowing from the load device. A processing circuit determines the input current from the positive rail to the load device based on the sense voltage.

Time modulation for DC-DC analog current sensing

A converter system includes a reference buffer buffering a reference input to produce a DAC reference, operating from a reference feedback voltage generated by a reference divider. A tail buffer generates a tail voltage from an input voltage generated from the DAC reference by a tail divider. An R-2R type DAC utilizes an R-2R ladder to generate a DAC output from a code. This ladder has a tail resistor coupled to the tail voltage. A feedback buffer buffers the DAC output to produce a converter reference. A DC-DC converter generates a DC output from a DC input, based upon a converter feedback voltage. A feedback divider coupled between the DC output and the converter reference generates the converter feedback voltage. Control circuitry selectively taps the reference divider to produce the reference feedback voltage (performing gain trimming) and selectively taps the tail divider to produce the input voltage (performing offset trimming).

Trimming procedure and code reuse for highly precise DC-DC converters

Disclosed herein is a DC-DC converter including a power section and a bootstrap circuit for driving the gate of the high-side transistor of the power section. The bootstrap circuit includes an adaptive clamp circuit that maintains a proper voltage differential across the bootstrap capacitor within the bootstrap circuit for recharge during off-times regardless of whether the mode of operation of the DC-DC converter continuous conduction mode (CCM), discontinuous conduction mode (DCM), or pulse-skip mode. This voltage differential is established as being between a bootstrap voltage and a voltage at a tap between the high and low side transistors of the power section. The adaptive clamp circuit maintains the bootstrap voltage as following the lesser of the output voltage and the voltage at the tap.

Dynamic bias for bootstrap recharge in discontinuous mode DC-DC converters

In start-up, current is sourced by a current source to a first plate of a first capacitor while a second capacitor is maintained at zero charge. In a subsequent first operating phase, current is sourced to a first plate of the second capacitor while a second plate of the first capacitor is connected to the first plate of the second capacitor. At the end of the first operating phase, the first capacitor is discharged. In a subsequent second operating phase, current is sourced to the first plate of the first capacitor while a second plate of the second capacitor is connected to the first plate of the first capacitor. At the end of the second operating phase, the second capacitor is discharged. Steady state operation of the circuit involves an alternation of the first and second operating phases interleaved with transition phases where the first and second capacitors are discharged.

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Olbia-Tempio, Italy

Marco Attanasio