Volterra Semiconductor Corporation

Maxim Integrated Products, Inc.

Infineon Technologies Canada Inc.

Marco A Zuniga

Budong You

Badredin Fatemizadeh

Yang Lu

Anthony J Stratakos

John Xia

Jun Ruan

David B Lidsky

Ilija Jergovic

Michael D McJimsey

Amit Paul

Alexandr Ikriannikov

Vijay Parthasarathy

Kaiwei Yao

Artin Der Minassians

Ana Borisavljevic

Chiteh Chiang

Jayasimha Prasad

Vipindas Pala

Adam Brand

Rajwinder Singh

Tom K Castro

Charles Nickel

Chi-Nung Ni

Craig Cassella

Hamza Yilmaz

Andrew J Burstein

Thomas William Macelwee

Abhishek Jain

Brett A Miwa

Urs H Mader

Ashutosh Ravindra Joharapurkar

Zhemin Zhang

Nan Xing

Edward MacRobbie

Ramesh G Karpur

Yalong Li

Lucas Andrew Milner

Robert Wayne Mounger

Rohan Samsi

Sridhar Ramaswamy

Min Xu

William Numann

Budong Yu

Vineet Unni

Claudio Andres Canizares

Ahmad Mizannojehdehi

Suraj Somashekara Kumar

Chi-Teh Chiang

Ashutosh Kumar

David B Liksky

Alexandr Ikiannikov

Llija Jergovic

A circuit that is capable of generating a negative voltage on a negative voltage supply node. The circuit includes a negative voltage generation circuit, an oscillator and an oscillator control signal generator. The negative voltage generation circuit generates a negative voltage on the negative voltage supply node in response to receiving a signal from the oscillator. The negative voltage generated by the negative voltage generation circuit depends upon the frequency of the signal from the oscillator. The oscillator control signal generator controls the frequency of the signal from the oscillator by sensing the negative voltage present on the negative voltage supply node, and by increasing or decreasing the frequency of the signal from the oscillator accordingly. Thus, charge is replenished to the negative voltage supply node to more closely match the drawing of charge from that negative voltage supply node, thereby more accurately generating the negative voltage.

Negative voltage generator

A current sense circuit that allows for accurate sensing of a power current that flows through a power transistor as the power transistor ages. The circuit includes the power transistor, a sense transistor and a pull-up component. The control nodes of the power transistor and the sense transistor are connected, causing the power transistor and sense transistor to be on or off simultaneously. The pull-up component is connected between the input node of the power transistor and the input node of the sense transistor. When power is provided to the pull-up component, and when each of the power transistor and sense transistor are off, the pull-up component forces a voltage present at the sense transistor input node to be approximately equal to a voltage present at the power transistor input node, causing the sense and power transistors to age together.

Current sensing by using aging sense transistor

A transistor structure that includes multiple heterojunction layer sets, each generating a two-dimensional electron gas (2DEG), such that the transistor structure has a stack of 2DEGs that may be used to conduct between source and drain. A terminal is provided proximate an uppermost 2DEG to control whether the uppermost 2DEG is continuous between a source contact and a source plug. A source plug connects the uppermost 2DEG with the next 2DEG, and a drain plug also connects the uppermost 2DEG with the next 2DEG. Thus, the gate terminal may control the flow of current in sub-surface 2DEGs between the source and drain.

Transistor structure using multiple two-dimensional channels

A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor including a breakdown voltage clamp includes a drain n+ region, a source n+ region, a gate, and a p-type reduced surface field (PRSF) layer including one or more bridge portions. Each of the one or more bridge portions extends below the drain n+ region in a thickness direction. Another LDMOS transistor includes a drain n+ region, a source n+ region, a gate, an n-type reduced surface field (NRSF) layer disposed between the source n+ region and the drain n+ region in a lateral direction, a PRSF layer disposed below the NRSF layer in a thickness direction orthogonal to the lateral direction, and a p-type buried layer (PBL) disposed below the PRSF layer in the thickness direction. The drain n+ region is disposed over the PBL in the thickness direction.

LDMOS transistors with breakdown voltage clamps

A lateral double-diffused metal-oxide-semiconductor transistor includes a silicon semiconductor structure and a vertical gate. The vertical gate include a (a) gate conductor extending from a first outer surface of the silicon semiconductor structure into the silicon semiconductor structure and (b) a gate dielectric layer including a least three dielectric sections. Each of the at least three dielectric sections separates the gate conductor from the silicon semiconductor structure by a respective separation distance, where each of the respective separation distances is different from each other of the respective separation distances.

LDMOS transistors including vertical gates with multiple dielectric sections, and associated methods

A multi-transistor device includes first and second lateral double-diffused metal-oxide-semiconductor field effect (LDMOS) transistors sharing a first p-type reduced surface field (RESURF) layer and a first drain n+ region. In certain embodiments, the first LDMOS transistor includes a first drift region, the second LDMOS transistor includes a second drift region, and the first and second drift regions are at least partially separated by the first p-type RESURF layer in a thickness direction.

Multi-transistor device including first and second LDMOS transistors having respective drift regions separated in a thickness direction by a shared RESURF layer

A lateral double-diffused metal-oxide-semiconductor field effect (LDMOS) transistor includes a silicon semiconductor structure, a dielectric layer at least partially disposed in a trench of the silicon semiconductor structure in a thickness direction, and a gate conductor embedded in the dielectric layer and extending into the trench in the thickness direction. The dielectric layer and the gate conductor are at least substantially symmetric with respect to a center axis of the trench extending in the thickness direction, as seen when the LDMOS transistor is viewed cross-sectionally in a direction orthogonal to the lateral and thickness directions.

LDMOS transistors and associated systems and methods

A current sense device includes a reference transistor for electrically coupling to a power transistor, a sense transistor for electrically coupling to the power transistor, and control circuitry. The control circuitry is configured to (a) control current through the sense transistor such that a voltage at the sense transistor has a predetermined relationship to a voltage at the power transistor, and (b) control current through the sense transistor according to one or more operating conditions at the reference transistor, to compensate for aging of the power transistor.

Current sense devices and associated methods

A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor includes a silicon semiconductor structure and a vertical gate. The vertical gate includes (a) a first gate conductor and a second gate conductor each extending from a first outer surface of the silicon semiconductor structure into the silicon semiconductor structure in a thickness direction, (b) a first separation dielectric layer separating the first gate conductor from the second gate conductor within the vertical gate, and (c) a gate dielectric layer separating each of the first gate conductor and the second gate conductor from the silicon semiconductor structure.

Transistors with dual gate conductors, and associated methods

A dual-gate, self-aligned lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor includes a silicon semiconductor structure, a lateral gate including a first dielectric layer and a first conductive layer stacked on the silicon semiconductor structure in a thickness direction, and a vertical gate. The vertical gate includes a second dielectric layer and a second conductive layer disposed in a trench of the silicon semiconductor structure, the second dielectric layer defining an edge of the lateral gate in a lateral direction. A method for forming a dual-gate, self-aligned LDMOS transistor includes (a) forming a vertical gate of the LDMOS transistor in a trench of a silicon semiconductor structure and (b) defining a lateral edge of a lateral gate of the LDMOS transistor using the vertical gate.

Self-aligned, dual-gate LDMOS transistors and associated methods

A voltage regulator includes a high-side device, a low-side device, and a controller. The high-side device includes first and second transistors each coupled between an input terminal and an intermediate terminal, where the first transistor has a higher breakdown voltage than the second transistor. The low-side device is coupled between the intermediate terminal and a ground terminal. The controller is configured to drive the high-side and low-side devices to (a) alternately couple the intermediate terminal to the input terminal and the ground terminal and (b) cause the first transistor to control a voltage across the second transistor during switching transitions of the second transistor.

Voltage regulators with multiple transistors

A lateral double-diffused metal-oxide-semiconductor field effect transistor includes a silicon semiconductor structure, first and second gate structures, and a trench dielectric layer. The first and second gate structures are disposed on the silicon semiconductor structure and separated from each other in a lateral direction. The trench dielectric layer is disposed in a trench in the silicon semiconductor structure and extends at least partially under each of the first and second gate structures in a thickness direction orthogonal to the lateral direction.

Growing community of inventors

Palo Alto, CA, United States of America

Marco A Zuniga