Texas Instruments Corporation

Marco A Gardner

Jerry Doorenbos

Dimitar Trifonov

Henry Litzmann Edwards

Ricky A Jackson

Debarshi Basu

Joe G Di Bartolomeo

Jerry L Doorenbos

An integrated circuit that includes a substrate, a photodiode, and a Fresnel structure. The photodiode is formed on the substrate, and it has a p-n junction. The Fresnel structure is formed above the photodiode, and it defines a focal zone that is positioned within a proximity of the p-n junction. In one aspect, the Fresnel structure may include a trench pattern that functions as a diffraction means for redirecting and concentrating incident photons to the focal zone. In another aspect, the Fresnel structure may include a wiring pattern that functions as a diffraction means for redirecting and concentrating incident photons to the focal zone. In yet another aspect, the Fresnel structure may include a transparent dielectric pattern that functions as a refractive means for redirecting and concentrating incident photons to the focal zone.

Integrated photodetector

A method is provided. A communication is received by an input pin of an IC over a single-wire bus, where the communication includes a command byte. If the command byte is an initialization command byte, a self-addressing operation is performed to identify a bus address for the IC. Alternatively, if the command byte is a data movement command byte, a data movement operation is performed. When data movement operation is performed, the bus interface of the IC is set from the transparent mode to the operational mode if an operation address from the command byte matches the bus address so that a register identified in the command byte can be accessed and data movement with the register can be performed.

Serial interface

Various systems and methods for temperature measurement are disclosed. For example, some embodiments of the present invention provide temperature measurement systems. Such temperature measurement systems include a variable current source and a diode connected transistor. The variable current source is capable of applying two or more distinct currents to the diode connected transistor. The currents result in a different base-emitter voltage on the diode connected transistor. The systems further include an n-factor coefficient register and an analog to digital converter. The analog to digital converter is operable to receive two of the base-emitter voltages created by applying the different currents, and to provide a digital output based at least in part on a value stored in the n-factor coefficient register and the two base-emitter voltages.

Systems and methods for temperature measurement using n-factor coefficient correction

Various systems and methods for pulse width modulated clocking in a temperature measurement are disclosed. For example, some embodiments of the present invention provide temperature measurement systems with a variable current source, a transistor, and a pulse width modulation circuit. The variable current source is operable to provide a first current and a second current that are applied to the transistor. A first base-emitter voltage occurs on the transistor when the first current is applied, and a second base-emitter voltage occurs on the transistor when the second current is applied. The first base emitter voltage is associated with a first sample period, and a second base-emitter voltage is associated with a second sample period. The pulse width modulation circuit provides a pulse width modulated clock including a combination of the aforementioned first period and second period.

Systems and methods for PWM clocking in a temperature measurement circuit

A differential amplifier includes a differential input pair (A) coupled to a folded cascode stage (B) and a common mode feedback circuit () including a tracking circuit (A) coupled to first (Vout) and second (Vout) outputs of the folded cascode stage (B). The first and second outputs are coupled to first terminals of first (A) and second (B) tracking capacitors which have second terminals on which a first common mode output signal (V) is produced and also are coupled to first terminals of third (A) and fourth (B) tracking capacitors, respectively, which have second terminals on which a second common mode output signal (V) is produced. The first and third tracking capacitors are discharged by first (A) and second (B) switches that directly couple the first and second outputs to first and second inputs of a common mode feedback amplifier (). A desired common mode output voltage (V) is applied to a third input of the common mode feedback amplifier. The switches are opened to cause the first and second common mode output voltages to be generated, causing a common mode feedback control signal (V) to be generated for biasing the folded cascode stage.

Common mode feedback for large output swing and low differential error

Various systems and methods for temperature measurement are disclosed. For example, some embodiments of the present invention provide methods for temperature measurement that include exciting a provided transistor with at least four sequential input signals of different magnitudes. In response, the transistor exhibits a sequence of output signals corresponding to the four sequential input signals. The sequence of output signals is sensed using a different gain for each of the output signals included in the sequence of output signals, and the output signals included in the sequence of output signals are combined such that the combined output signals eliminates a resistance error. The combined output signals are then used to calculate a temperature of the transistor.

Systems and methods for resistance compensation in a temperature measurement circuit

Various systems and methods for capturing data are disclosed. For example, some embodiments of the present invention provide methods for performing a first analog to digital conversion using a delta-sigma based analog to digital converter, and performing a second analog to digital conversion using a SAR based analog to digital converter. The delta-sigma converter provides a first portion of a conversion result, and the SAR based analog to digital converter provides a second portion of the conversion result. The methods further include combining the first portion of the conversion result with the second portion of the conversion result to produce a combined conversion result.

Hybrid delta-sigma/SAR analog to digital converter and methods for using such

The synchronous logic device with reduced pin count scan chain includes: more than two flip/flops coupled to form a shift register for receiving a scan data input signal; a combinational logic circuit for receiving device inputs, generating flip/flop inputs for the more than two flip/flops, and generating an output signal; a first multiplexer for providing a clock signal to the more than two flip/flops during a test mode; a second multiplexer for selecting between a test mode output from the shift register and the output signal from the combinational logic circuit, and for providing a scan data output signal; and wherein the scan data input signal and the scan data output signal share an input/output pin.

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Tucson, AZ, United States of America

Marco A Gardner