Intel Corporation

Marcin Andrzej Chrapek

Reshma Lal

An apparatus includes a central processing unit (CPU), including a plurality of processing cores, each having a cache memory, a fabric interconnect coupled to the plurality of processing cores and cryptographic circuitry, coupled to the fabric interconnect including mesh stop station to receive memory data and determine a destination of the memory data and encryption circuitry to encrypt/decrypt the memory data based on a destination of the memory data.

Cache optimization mechanism

An apparatus comprising translator circuitry to receive a plurality of physical addresses of memory data, determine an offset associated with each of the physical page addresses and apply a tweak seed to each offset to generate a plurality of tweaks.

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Zurich, Switzerland

Marcin Andrzej Chrapek