Intel Corporation

Marcelo Yuffe

Tsvika Kurts

Doron Orenstien

Jeffrey R Wilcox

Doron Orenstein

Noam Yosef

Alex Waizman

Ziv Shmuely

Todd M Witter

Zelig Wayner

Arie Bernstein

Sean T Baartmans

Marcus R Winston

Rony Ghattas

Eilon Hazan

A processing device comprises a debug port controller to monitor operations of the processing device to determine whether the processing device is operating in a first mode or a second mode and to collect trace information comprising operating characteristics of the processing device. The processing device further comprises a display engine logic to process display data for output to a display device. In addition, the processing device comprises a display engine interface to provide, to a plurality of existing platform connectors, the display data from the display engine logic when the processing device is operating in the first primary mode and the trace information from the debug port controller when the processing device is operating in the second mode as determined by the debug port controller.

High-speed debug port using standard platform connectivity

Methods and systems provide for a semiconductor die that is compatible with a wide variety of industry standard sockets, where each type of socket is identified by a different pin map. In one embodiment, the die has a plurality of signal lines, one or more surface contacts and one or more signal selectors coupled to the signal lines and the surface contacts. Each signal selector electrically connects one of the signal lines to one of the surface contacts based on a programming signal. In a particularl embodiment, each signal selector includes a multiplexer and a fuse element, where the multiplexer routes one of its input ports to its output port based on a programming value of the fuse element. The programming value can be set by the programming signal.

Programming semiconductor dies for pin map compatibility

A bus agent is described having a controller to cause assertion of a power signal if an address is to be transferred to a receiving bus agent, the power signal to enable a set of input address sense amplifiers of the receiving agent, prior to the receiving bus agent receiving the address.

Apparatus and method for address bus power control

An approach for data bus power control. Data input sense amplifiers of a request agent are enabled prior to a data phase of a transaction according to a data bus power control signal. Once enabled, the data input sense amplifiers can capture data provided during the data phase of the read transaction. Accordingly, the data input sense amplifiers of the request agent are disabled according to the power control signal once the data phase of the read transaction is complete.

Apparatus and method for data bus power control

For one embodiment, a computer system includes both high power and low power buses coupling a processor to a controller. When the processor is in a high power mode, its cache is snooped by the controller via the high power bus. When the processor is in a low power mode, its cache is snooped by the controller via the low power bus.

Method and apparatus for communicating between integrated circuits in a low power mode

A method is described that involves driving a first current through a line and a termination resistance so that a logical value on the line changes from a first logical value to a second logical value. The method also includes holding the second logical value on the line by driving a second current through the line and the termination resistance where the second current less than the first current. An apparatus is described that includes a driver that drives a first current through a line and a termination resistance so that a logical value on the line changes from a first logical value to a second logical value. The driver holds the second logical value on the line by driving a second current through the line and the termination resistance. The second current is less than said first current.

Apparatus and method for power efficient line driver

A circuit for driving and receiving signals on a bus line includes a pull-up switch and a pull-down switch. The pull-up switch has an impedance that matches the characteristic impedance of the bus line. The pull-down switch has an impedance of about half of the characteristic impedance of the bus line. When the circuit is receiving a signal or driving a logic high signal on the bus line, the pull-up switch is enabled so that the bus line voltage is pulled up, while the pull-down switch is disabled to prevent the pull-down switch from pulling down the bus line voltage. When the circuit is driving a logic low signal on the bus line, the pull-down switch is enabled so that the bus line voltage is pulled down, while the pull-up switch is disabled to prevent the pull-up switch from pulling up the bus line voltage.

Growing community of inventors

Binyamina, Israel

Marcelo Yuffe