Cselt-centro Studi E Laboratori Telecomunicazioni S.p.a.

Marcello Melgara

Giuseppe N Capizzi

Cesario Cianci

Maurizio Paolini

Maura Torolla

The control unit detects the errors concurrently with normal microinstruction execution through suitable internal checking circuits and a determined microinstruction allocation in the memory. Microinstructions comprise additional fields (CS, FS) carrying the encoding, in Modified Berger code, of the allocation address of the microinstruction itself and of the following one. The microinstructions of destination of conditional jumps are allocated so that their codes are related to each other by simple logic relationships which are then reproduced by an internal circuit (CSM). The two fields, the one of the next microinstruction being duly delayed, are then compared and possible differences represent unidirectional and incorrect sequencing errors. The other errors are detected through particular implementations of some internal circuits (STK1, INC1) and duplication of others (RCT, SEL).

MOS selfchecking microprogrammed control unit with on-line error

Speech synthesis is selectable in two modes: 'normal' mode in which the synthesis filter is responsive to prestored parameters, and 'test' mode which executes a checking procedure based on test words from an outside source. Each mode has corresponding instructions prestored in a memory.

Digital speech synthesizer

A circuit arrangement for deciding concurrent requests for access to a common data bus emitted by a number n=2.sup.m of components of different ranks, specifically multiprocessor elements, comprises n mutually identical arbitration devices respectively associated with these components. The arbitration devices are interconnected in a chain by a priority bus of branched binary structure divided into m lines connected, within each device, to a logic network that is also connected to an internal m-conductor bus extending from a priority-code register. The priority bus, whose lines are normally at zero potential, is connected in any given device to the register thereof in the presence of an access request from the associated component whereupon its logic network determines whether the code on that bus equals the contents of the register; if so, the associated component is enabled by a control unit of the device to access the data bus. If, however, a simultaneous access request from a higher-ranking component causes another arbitration device to energize the priority bus, the code emitted by that other device overrides that of the first-mentioned device whose logic network therefore detects an inequality. A cascaded connection of the control units of the several arbitration devices enables a decrementer in each device to establish priority codes of progressively lower rank along the cascade in an initialization phase; the logic network also modifies, at the beginning of each operating cycle except during prolonged seizure of the data bus by any component, the priority code initially assigned to each arbitration device in order to give precedence to nominally lower-ranking components.

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Valenza, Italy

Marcello Melgara