Micron Technology Incorporated

Intel Corporation

Marcello Mariani

Giorgio Servalli

Antonino Rigano

Alessandro Grossi

Andrea Locatelli

Carlo Pozzi

Durai Vishak Nirmal Ramaswamy

Fabio Pellizzer

Paolo Tessariol

Anna Maria Conti

Livio Baldi

Sara Vigano

Paolo Giuseppe Cappelletti

Giulio Albini

Augusto Benvenuti

Umberto Maria Meotto

Gianpietro Carnevale

Paola Bacciaglia

Andrea Filippini

Marcello Calabrese

Luca Ferrario

Michele Magistretti

Federica Zanderigo

Luca Di Piazza

Enzo Carollo

Sara Marelli

Micaela Gabriella Tomasini

Agostino Pirovano

Lorenzo Fratin

Angelo Visconti

Roberto Bez

Alessandro Calderoni

Lorena Beghin

Anna Rita Odorizzi

Methods, systems, and devices for formation for memory cells are described. A semiconductor device (e.g., a memory die) may include asymmetrical rows of conductive pillars and one or more dielectric materials. For example, the memory die may include a set of conductive pillars that are arranged in rows that are asymmetrically spaced. Here, a first row of conductive pillars may be a first distance away from a second row of conductive pillars and a second, larger distance away from a third row of conductive pillars. Additionally, the memory die may include one or more dielectric materials. In some cases, when depositing a dielectric material as part of a self-aligning process, the material may conformally line exposed surfaces according to a substantially uniform depth, which may decrease a subsequent quantity of masking operations to form the memory die.

Formation for memory cells

Some embodiments include an integrated assembly having pillars arranged in an array. The pillars have channel regions between upper and lower source/drain regions. Gating structures are proximate to the channel regions and extend along a row direction. Digit lines are beneath the pillars, extend along a column direction, and are coupled with the lower source/drain regions. Linear structures are above the pillars and extend along the column direction. Bottom electrodes are coupled with the upper source/drain regions. The bottom electrodes have horizontal segments adjacent the upper source/drain regions and have vertical segments extending upwardly from the horizontal segments. The vertical segments are adjacent to lateral sides of the linear structures. Ferroelectric-insulative-material and top-electrode-material are over the bottom electrodes. A slit passes through the top-electrode-material, is directly over one of the linear structures, and extends along the column direction.

Memory devices and methods of forming memory devices

Some embodiments include an integrated assembly having first and second pillars of semiconductor material. The first pillar includes a first source/drain region, and the second pillar includes a second source/drain region. First and second bottom electrodes are coupled with the first and second source/drain regions, respectively. The first and second source/drain regions are spaced from one another by an intervening region. First and second leaker-device-structures extend into the intervening region from the first and second bottom electrodes, respectively. Top-electrode-material extends into the intervening region and contacts the first and second leaker-device-structures. Ferroelectric-insulative-material is between the top-electrode-material and the bottom electrodes. Some embodiments include methods of forming integrated assemblies.

Integrated assemblies and methods of forming integrated assemblies

Some embodiments include an integrated assembly having digit lines supported by a base and extending along a first direction. A shield-connection-line is supported by the base and extends along the first direction. Transistor active regions are over the digit lines. Each of the active regions includes a channel region between an upper source/drain region and a lower source/drain region. The lower source/drain regions are coupled with the digit lines. Capacitors are coupled with the upper source/drain regions. Wordlines extend along a second direction which crosses the first direction. The wordlines include gate regions adjacent the channel regions. Shield lines extend along the second direction. The shield lines are above the digit lines and are coupled with the shield-connection-line.

Integrated assemblies having shield lines between neighboring transistor active regions

Some embodiments include an integrated assembly having first and second pillars of semiconductor material laterally offset from one another. The pillars have source/drain regions and channel regions vertically offset from the source/drain regions. Gating structures pass across the channel regions, and extend along a first direction. An insulative structure is over regions of the first and second pillars, and extends along a second direction which is crosses the first direction. Bottom electrodes are coupled with the source/drain regions. Leaker-device-structures extend upwardly from the bottom electrodes. Ferroelectric-insulative-material is laterally adjacent to the leaker-device-structures and over the regions of the bottom electrodes. Top-electrode-material is over the ferroelectric-insulative-material and is directly against the leaker-device-structures. Some embodiments include methods of forming integrated assemblies.

Methods, systems, and devices for differential storage in memory arrays are described. A memory device may include pairs of memory cells configured to store a single logic state (e.g., a single bit of information). Additionally, the memory device may include sense amplifiers configured to sense the logic state based on a difference between a voltage of a first ferroelectric memory cell of the pair of memory cells and a voltage of a second ferroelectric memory cell of the pair of memory cells. In one example, the memory device may include pairs of memory cells within a single memory array on a single level. Here, each memory cell pair may include a memory cells that are each coupled with a same word line and plate line. Additionally, each memory cell pair may include memory cells each coupled with different digit lines.

Differential storage in memory arrays

Some embodiments include an integrated assembly having a pillar of semiconductor material. The pillar has a base region, and bifurcates into two segments which extend upwardly from the base region. The two segments are horizontally spaced from one another by an intervening region. A conductive gate is within the intervening region. A first source/drain region is within the base region, a second source/drain region is within the segments, and a channel region is within the segments. The channel region is adjacent to the conductive gate and is vertically disposed between the first and second source/drain regions. Some embodiments include methods of forming integrated assemblies.

Integrated transistors having gate material passing through a pillar of semiconductor material, and methods of forming integrated transistors

Some embodiments include an integrated assembly having a first bottom electrode adjacent to a second bottom electrode. An intervening region is directly between the first and second bottom electrodes. Capacitor-insulative-material is adjacent to the first and second bottom electrodes. The capacitor-insulative-material is substantially not within the intervening region. Top-electrode-material is adjacent to the capacitor-insulative-material. Some embodiments include methods of forming integrated assemblies.

Methods, systems, and devices for techniques to manufacture ferroelectric memory devices are described. In some cases, a memory array may be manufactured using a self-aligned manufacturing technique. For example, a continuous layer of dielectric material may be formed over an assembly which includes an array of transistors coupling contacts on the surface of the assembly with a set of digit lines. In some cases, an array of cavities may be etched into the dielectric material, each cavity exposing a set of contacts. A set of bottom electrodes corresponding to the set of contacts may be formed on sidewalls in each cavity, for example by depositing a layer of electrode material and etching the electrode material using a variety of hard masks.

Techniques to manufacture ferroelectric memory devices

Some embodiments include an assembly having first and second pillars. Each of the pillars has an inner edge and an outer edge. A first gate is proximate a channel region of the first pillar. A second gate is proximate a channel region of the second pillar. A shield line is between the first and second pillars. First and second bottom electrodes are over the first and second pillars, respectively; and are configured as first and second angle plates. An insulative material is over the first and second bottom electrodes. The insulative material may be ferroelectric or non-ferroelectric. A top electrode is over the insulative material. Some embodiments include methods of forming assemblies.

A method of forming a memory device having magnetic tracks individually comprising a plurality of magnetic domains having domain walls, includes forming an elevationally outer substrate material of uniform chemical composition. The uniform composition material is partially etched into to form alternating regions of elevational depressions and elevational protrusions in the uniform composition material. A plurality of magnetic tracks is formed over and which angle relative to the alternating regions. Interfaces of immediately adjacent of the regions individually form a domain wall pinning site in individual of the magnetic tracks. Other methods, including memory devices independent of method, are disclosed.

Memory devices comprising magnetic tracks individually comprising a plurality of magnetic domains having domain walls and methods of forming a memory device comprising magnetic tracks individually comprising a plurality of magnetic domains having domain walls

Implementations described herein relate to various structures, integrated assemblies, and memory devices. In some implementations, an integrated assembly includes a pillar having an upper source/drain, a middle source/drain, a lower source/drain, an upper channel between the upper source/drain and the middle source/drain, and a lower channel between the middle source/drain and the lower source/drain. The integrated assembly includes a gate pair that includes a first gate and a second gate. The first gate is positioned on a first side of the pillar at a first height, and the second gate is positioned on a second side of the pillar, that is opposite the first side, at a second height that is different from the first height. The integrated assembly includes a capacitor that is electrically coupled with the upper source/drain. Some implementations include methods of forming the various structures, integrated assemblies, and memory devices.

Growing community of inventors

Milan, Italy

Marcello Mariani