Sgs-thomson Microelectronics S.r.l.

Stmicroelectronics S.r.l.

Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno

Marcello Leone

Giona Fucili

Maurizio Nessi

Annamaria Rossi

Roberto Gariboldi

Rinaldo Castello

Patrizia Milazzo

Alberto Gola

A successive approximation register has a serial input and output comprises a chain of logic circuits of the bistable type which have selectable input terminals feedback connected by a storage and control element and logic gate circuits of the OR-type, and connected to a serial line through respective internal switches communicating the serial line to input terminals of the logic circuits in said chain, the serial line forming an input to a flip-flop of the D type which is the output element of the register.

Successive approximation shift register with reduced latency

A toggle flip-flop with reduced integration area, comprising a flip-flop of the D-type with an inverting input stage and a master-slave portion. Three transistors connected to the inverting stage form a logic gate of the XOR type whereto the output terminal of the master-slave portion is fed back.

Toggle flip-flop network with a reduced integration area

A digital-to-analog converter includes a potentiometric string suitable for realizing a relatively high number of bits that significantly reduces the silicon area requirement and simplifies mismatch compensation. The structure includes a first resistance string to realize a first DAC to convert a first number of most significative bits, and a second potentiometric string functionally connected in cascade to the first, but realized with MOS transistors. The structure of the invention allows the coupling of the two DACs in cascade by exploiting the MOS transistors that form the second potentiometric string, that is, the second DAC, thus avoiding the use of operational switches or amplifiers which may provide error sources. Moreover, the structure of the invention lends itself to the implementation of efficient compensation circuits for integral and differential linearity errors.

Compensated MOS string and DAC employing such a potentiometric string

A sense and protection circuit against short circuits for digital outputs, comprising a logic gating circuit of the exclusive OR type (EX1) which has a first input terminal connected to a signal input node (IN) and an output terminal which is connected to an input terminal of a signal level shifter output stage (B). A second logic gating circuit of the exclusive OR type (EX2) has a first input terminal connected to the input node (IN) and a second input terminal connected, through an inverting circuit (IN1), to an output terminal (OUT) of the output stage (B). A second input terminal of the first logic gate circuit is coupled to an output terminal of the second logic gate circuit through a comparator circuit (SCH1) and a delay circuit means (C,R,D).

Circuit for detection and protection against short circuits for digital

A drive circuit includes a voltage source supplying a reference voltage at its output; a voltage elevating circuit connected to a supply voltage and to the output of the voltage source, and supplying at its output, under normal operating conditions, a drive voltage greater than the supply voltage and increasing with the reference voltage. The input of the voltage source is connected to the output of the voltage elevating circuit, and defines a positive feedback path resulting in an increase in the reference voltage corresponding to an increase in the drive voltage, and therefore results in a corresponding increase in the drive voltage up to a maximum permissible value, thus providing for a sufficient drive voltage for driving the gate-source junction of power MOS transistors, even in the presence of a low supply voltage.

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Rho, Italy

Marcello Leone