Nxp B.v.

Marcello Ganzerli

Lucien Johannes Breems

Yu Lin

Chenming Zhang

Pierluigi Cenci

Gerrit Willem Den Besten

Konstantinos Doris

Georgi Ivanov Radulov

Mingda Huang

Marios Neofytou

Pavlos Athanasiadis

A system and method of replicating and cancelling chopping folding error in delta-sigma modulators. The modulator may include a loop filter coupled to a quantizer providing a digital signal, chopper circuitry that chops analog signals of the loop filter at a chopping frequency, and chopping folding error cancellation circuitry that replicates and cancels a chopping folding error of the chopper circuitry to provide a corrected digital signal. A digital chopper or multiplier chops the digital signal to provide a chopped digital signal, and the chopped digital signal is either amplified or multiplied by a gain value or digitally filtered to replicate the chopping folding error, which is then subtracted from the digital signal for correction. The timing and duty cycle of the chopping frequency may be adjusted. Timing and duty cycle adjustment may be calibrated along with the filtering.

System and method of replicating and cancelling chopping folding error in delta-sigma modulators

A sigma delta modulator comprises an input configured to receive an input analog signal; a summing junction configured to subtract a feedback analog signal from the input analog signal; a first stage including a low pass filter coupled to the summing junction, wherein the low pass filter is configured to generate a first filtered signal; a second stage coupled to the low pass filter, configured to generate a second filtered signal by an active filter; a back-end stage coupled to the second stage, wherein the back-end stage comprises an analog to digital converter configured to convert the 2filtered signal to a digital output signal by sampling at a predetermined sampling frequency (fs); and a feedback path for routing the digital output signal to the summing junction, wherein the feedback path comprises a digital to analog converters, DAC, converting the digital output signal to the feedback analog signal.

Sigma delta modulator and method therefor

A wireless transceiver system includes a transmitter and a receiver. The transmitter includes a digital processor and a self-correction modulator coupled to the digital processor, wherein based upon a calibration correction assessment of an in-phase (I) signal and a quadrature (Q) signal received from the digital processor, the self-correction modulator generates a calibrated modulated signal. The self-correction modulator includes a core modulator and a calibration correction unit. The calibration correction unit is configured to correct an output of the core modulator based upon the calibration correction assessment. The calibration correction unit includes a calibration processing unit and a calibration modulator, wherein the calibration processing unit provides correction quantities that are used to program the calibration modulator to provide the self-corrected modulated signal.

Systems and methods for calibration of in-phase/quadrature (I/Q) modulators

A communication unit, such as a radar unit () includes a plurality of cascaded millimetre wave, mmW, transceiver, TRx, circuit, each comprising at least one phase shift circuit () and each coupled to respective antennas; and a signal processor circuit () operably coupled to the plurality of cascaded mmW TRx circuits and configured to process transmit and receive signals of the plurality of cascaded mmW TRx circuits. The radar unit () further comprises: a first TRx circuit () of the plurality of cascaded mmW TRx circuits being configured to wirelessly transmit () a signal to a second TRx circuit () via a respective antenna; a localization processing circuit () operably coupled to at least one of the first TRx circuit () and second TRx circuit () and configured to wirelessly determine a distance relationship () between at least one antenna coupled to the first TRx circuit () and at least one antenna coupled to the second TRx circuit (); and a phase control unit (), operably coupled to the localization processing circuit () and configured to adjust at least one phase shifter () in response to the wirelessly determined distance relationship.

Communication unit, integrated circuits and methods for cascading integrated circuits

The present application relates to a reconfigurable analog front-end circuit and a reconfigurable Ethernet transceiver with a reconfigurable analog front-end circuit. The circuit is reconfigurable using the at least one signal-path switching element controlled by a mode signal to operationally establish a first or a second signal path. The first signal path comprises an optional first signal-conditioning section and a shared ADC. The second signal path comprises an optional second signal-conditioning section, an upstream ADC and the shared ADC. The signal paths are selectively switched in response to a mode signal.

Reconfigurable Ethernet receiver and an analog front-end circuit thereof

Circuits, apparatus, and methods are disclosed for decision feedback equalization. In one embodiment, an apparatus includes a plurality of time-interleaved slices for processing an input data stream. Each of the slices includes a sampler circuit, a multiplexer, and a latch. In each slice, the multiplexer and the sampler circuit provide sampled output data corresponding to one of a plurality of different versions of the input data stream at times designated uniquely for the slice, according to one or more selection signals. The selection signals are derived from a output of the multiplexer of at least one other of the time-interleaved slices. The latch provides a controlled output in response to the multiplexer and the sampler circuit, as a function of the designated unique times.

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Eindhoven, Netherlands

Marcello Ganzerli