Nxp B.v.

U.S. Philips Corporation

Marcel J Pelgrom

Maarten Vertregt

Hendricus J M Veendrick

Violeta Petrescu

Atul Katoch

Thomas Suwald

Victor Zieren

Robert Meyer

Hendricus Joseph Maria Veendrick

Hans Paul Tuinhout

Jurgen H Geerlings

Nobuji Negishi

Praveen Pavithran

Jean Wieling

Hendricus Joseph Veendrick

Hendrickus Joseph Maria Veendrick

Raymond Speer

Apparatus and method for IR-drop and supply noise measurements in electronic circuits. A first voltage at a point of interest in the circuit is sampled and stored during a quiescent mode of the circuit the voltage is to be measured in. Subsequently, the circuit is brought in an operating mode and a second voltage is sampled and held at the same point of interest. The first and the second voltage are compared and a corresponding voltage signal is passed to a system output.

Simple and stable reference for IR-drop and supply noise measurements

The invention discloses an integrated circuit () for securely storing a codeword. The value of the codeword is dependent on the mobility (&#x3bc;A, &#x3bc;B, &#x3bc;C) of at least one transistor (TRA, TRB, TRC) of the integrated circuit. The invention further discloses a reader means (), a method for determining the value of the codeword from the integrated circuit (), and a method for altering the value of the codeword.

Secure storage of a codeword within an integrated circuit

An integrated circuit comprises a plurality of sensing circuits (), each for detecting whether a respective physical operating parameter is above or below a respective reference value. The integrated circuit contains a serial shift register () for shifting digital data signals that represent the respective reference values from a successive approximation update circuit () to the sensing circuits () and back to the successive approximation update circuit (). Detection results of the sensing circuits () are shifted to the successive approximation update circuit () with the digital data signals. The successive approximation update circuit () is used to form the digital data so that the reference values form successive approximations of the physical operating parameter values during an analog to digital conversion process. In this way the successive approximation update circuit () is shared by a plurality of sensing circuits ().

Monitoring physical operating parameters of an integrated circuit

The present invention relates to a on-chip circuit for on silicon interconnect capacitance (Cx) extraction that is self compensated for process variations in the integrated transistors. The circuit () comprises signal generation means () for generating a periodical pulse signal connected to first and to second signal delaying means () for respective delaying said pulse signal, wherein said second signal delaying means () are configured to have a delay affected by said interconnect capacitance (Cx); a logical XOR gate () for connecting respective first and said second delay signals of said respective first and second delay means (), said logical XOR gate () being connected to signal integrating means (); and said signal integrating means () being connected to analog to digital converting means (). Whilst the error in conventional uncompensated systems, like delay line only, the error can be up to 30%, in the circuit according to the invention, the error due to process variations in the front-end is about 2%. Further, an output is provided in a digital format and thus, can be measured quickly with simple external hardware. Furthermore, the pulse signal frequency can be used as a monitor to measure process variations in the front-end. Moreover, since the circuit () is remarkably accurate and very easy to measure, it is the best choice as a process monitor for every chip fabricated in the future.

On silicon interconnect capacitance extraction

An integrated circuit () comprises a monitor (M, M, M) operable to produce monitor data in dependence upon a measured parameter of the integrated circuit (); and a self test controller () connected to receive monitor data from the monitor (M, M, M). The self-test controller is also operable to output self test data from the integrated circuit. The monitor includes an output shift register (SR, SR, SR) and is operable to output monitor data through the shift register (SR, SR, SR). Such a system enables simplified communication of system self test results on an integrated circuit.

Intergrated circuit self-test architecture

A flash analog-to-digital converter comprises a resistive string powered by a reference voltage source for providing a set of equidistant reference voltages and a set of comparators for comparing the analog input signal with the reference voltages. A set of switches are arranged and controlled to perform an algorithm for mitigating the influence of mismatches between the components. The switches are arranged between the reference voltage source and the resistive string so that switches in the reference inputs to the comparators are avoided. The resistive string is preferably circular. The converter can handle differential signals.

Flash analog-to-digital converter

An integrated circuit is provided with a distributed supply voltage monitoring system in which a single controller controls a plurality of voltage monitors located in respective modules of the integrated circuit. The controller and each circuit form a successive approximation analogue to digital converter Such a system enables a small size monitoring circuit to be realized for every module of the integrated circuit.

Supply voltage monitoring

A digital-to-analog converter having a ladder resistor portion for generating a plurality of quantization signals of predetermined values based on reference signals of predetermined values and a quantization switch portion for selectively outputting one of the quantization signals in accordance with a digital input value. The ladder resistor portion is coupled to at least one resistor for generating a signal of a value which corresponds to a desired signal level of a signal to be added. A switch provided for supplying the signal of the value corresponding to the desired signal level to an output of the switch portion in response to a timing signal synchronized with the signal to be added.

Digital-to-analog converter

For a comb filter arrangement, for example, for separating a color picture signal into a modulated chrominance subcarrier and a luminance signal, while generating two comb filter function, a one-stage median filter (21) is provided in which the amplitudes of the simultaneously available signals of three picture lines and the two comb filter functions are compared with each other in a comparator stage which supplies logical comparison signals to a selection logic (30) in dependence upon the comparison results. The selection logic (30) constantly determines the signal having the middle instantaneous amplitude of the signals applied to the comparator stage on the basis of the comparison signals, and applies this signal to the medium filter output.

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Eindhoven, Netherlands

Marcel J Pelgrom