Altera Corporation

Marcel A LeBlanc

Andy Louie Lee

Vaughn Betz

Ryan Fung

Gary Lai

Chong H Lee

James G Schleicher

Vinson Chan

Neville Carvalho

Binh Ton

Thiagaraja Gopalsamy

Razmik Ahanessians

Clock switch-over circuits and methods provide clock signals to clock routing networks. According to one embodiment, a multiplexer selects between a first clock signal and a second clock signal in response to a switch select signal received from a control circuit. A storage circuit stores an enable signal in response to an output clock signal of the multiplexer. A logic circuit transmits the output clock signal of the multiplexer to a clock routing network in response to the enable signal from the storage circuit. At least one signal is transmitted from the clock switch-over circuit to the control circuit.

Clock switch-over circuits and methods

A synchronous clear emulation circuit is provided. The synchronous clear emulation circuit includes a register having an asynchronous clear port. Moreover, the synchronous clear emulation circuit is configured to emulate a synchronous clear port by using the asynchronous clear port. The synchronous clear port is emulated by outputting a data output signal that is synchronous with the clock signal and the data output signal is based on an asynchronous clear signal received at the asynchronous clear port. The asynchronous clear port performs a function of the asynchronous clear port without the synchronous clear port implemented within the register.

Methods and systems for emulating a synchronous clear port

A megafunction block is provided that includes a serial interface enabling a user to specify settings of a configurable block of a programmable logic device. The megafunction block includes a register array having the capability of translating address information into actual addresses for a memory of the configurable block. Thus, as future configurations/standards are developed that a programmable logic device with the megafunction block will interfaces with, the settings for interfacing with the standards may be added to the register array. Consequently, the pin count will not need to increase as the megafunction block is scalable through the register map. Control logic verifies that the translated address is a valid address and the control logic will generate a selection signal based on whether a read or write operation is to be performed.

Megafunction block and interface

An interface for a programmable logic device having a non-volatile memory where a portion of the non-volatile memory is user accessible is provided. A megafunction provides the electronic circuit designer with interface protocol options for the user accessible portion of the non-volatile memory block. The circuitry associated with the user selected interface is then programmed into the programmable logic device.

User non-volatile memory interface megafunction

Disclosed is a device and method for configuring a register in a PLD to operate as a logical AND gate. So configuring a register allows it to be used in a multiplication carried out by the PLD. A logic element includes a combinatorial logic section and at least one register interconnected with the combinatorial logic section. The register is configured to operate as a logical AND gate. The logic element can include a data input, a clear input, and a load input wherein the load input can be held high, a first bit to be ANDed can be input on the data input and a second bit to be ANDed can be input on the clear input. The logic element can, for example be configured to carry out at least a portion of a multiplication of a multiplicand and a multiplier.

Computer combinatorial multipliers in programmable logic devices

Protected electronic designs permit appropriate simulation and testing of the electronic design in a simulation environment, while preventing a correctly operating unauthorized implementation of the electronic design in a hardware environment such as a programmable device. An unprotected version of the simulation version of an electronic design is augmented by adding protection circuitry to the unprotected version to create a protected version of the electronic design, which operates correctly in a simulation environment but which fails to operate correctly in a hardware environment. In some embodiments of the present invention, a separate programming version which does not incorporate the protection circuitry of the simulation version may also be provided for licensed/authorized users of the electronic design, which may be an IP core or other design.

Electronic design protection circuit

A random access memory array is used as a shift register. Data is written into different locations in a first column of the memory and then gradually transferred successively to any other number of columns in the memory. Such column-to-column data transfer is the result of reading data from each column and presenting it for writing in the next column. To compensate for latency (delay) in the column-to-column data transfer, the circuitry that controls reading is kept ahead of the circuitry that controls writing by a number of read/write cycles that takes approximately the same amount of time as the column-to-column data transfer delay.

Memory implementations of shift registers

Software modules referred to as &ldquo;plug-ins&rdquo; associate with megafunctions written in any Hardware Description Language to provide rich parameterization. To the user, the plug-ins present a &ldquo;wizard&rdquo; interface allowing selection or setting of any number of important parameters for a particular megafunction. To the design compiler, parameterized megafunctions instantiated via a plug-in appear non-parameterized functions of a type that may be easily handled (by, for example, VHDL and Verilog compilers). Plug-ins &ldquo;plug into&rdquo; a compiler or an application associated with the compiler, sometimes referred to as a &ldquo;plug-in manager.&rdquo; The plug-in manager creates compilable files from user-defined parameter settings passed by the plug-ins.

Method of generating customized megafunctions

A method of analyzing a plurality of signal propagation delays along a plurality of signal interconnection lines within a programmable integrated circuit using a distributed electrical circuit model for the signal interconnection lines which programmably interconnect the electronic circuits forming the cooperative logic functions within the programmable integrated circuit. Load models representing such electronic circuits are incorporated into the circuit model for the signal interconnection lines, and differential nodal equations are generated in accordance with Kirchhoff's Current Law. The differential equations are converted to linear equations in which time is expressed in terms of a finite time interval, or time step. The linear equations are simplified by using substitution techniques for the common variables, thereby producing simplified linear nodal equations which can be collectively represented in a matrix format which includes a square quasi-diagonal coefficient matrix in which all elements more than one element away from the major diagonal thereof have a zero value. Such simplified linear nodal equations can be quickly and easily solved to compute the signal propagation delays along the signal interconnection lines, thereby facilitating any necessary redesign of such signal interconnection lines so as to reduce critical signal propagation delays.

Fast modeling of signal propagation delays through interconnect wires

Circuitry is provided that allows a register without an asynchronous loading capability to be asynchronously loaded. Logic gates are provided before and after the register. The logic gates are driven by an output signal from a storage circuit such as a latch. When the output signal has one value the logic gates act as non-inverting buffers. When the output signal has another value the logic gates act as inverters. The circuitry allows the normal synchronous operations of the register to be maintained. A hazard coverage circuit can be provided to prevent glitches from appearing at the output during asynchronous operations. The logic gates may be formed from exclusive OR gates implemented in programmable logic on a programmable logic device.

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Sunnyvale, CA, United States of America

Marcel A LeBlanc