Thomson-Csf

E2v Semiconductors

Thomson-Csf Semiconducteurs Specifiques

Atmel Grenoble S.a.

Marc Wingender

St&eacute;phane Le Tual

Stephane Le Tual

Laurent Simony

François Bore

Sandrine Bruel

Christophe Gaillard

Emmanuel Dumaine

Francois Bore

Fran&ccedil;ois Bore

The invention relates to digital-to-analog converters for converting current. The converter includes a pair of differential branches with two transistors controlled by a digital register activated at a clock frequency, and two resistive loads receiving the currents of the differential branches to produce a differential electrical signal representing the analog result of the conversion. The converter includes a dual switching circuit for the currents of the differential branches: a first switching circuit enables the transmission of the currents of the differential branches toward the loads for 70% to 95% of the clock period and shunts these currents outside the loads for the rest of the time; a second switching circuit alternately and symmetrically makes a direct link followed by a cross link between the differential branches and the loads. The converter provides a signal with high spectral purity and can work with a good level of power in the four Nyquist zones of the spectrum of the output analog signal, and notably in the second and third zones.

Digital-to-analogue converter

The invention relates to integrated circuits comprising a set of identical differential pairs of two transistors each (T, T; T, T) one receiving a variable voltage (Vinp, Vinn) at its base and the other receiving a fixed reference voltage (Vrefp, Vrefn). In order to reduce the dispersion of the offset voltages of said differential pairs, it is provided that the transistor (T, T) that receives a fixed reference voltage has an emitter surface at least twice as large as the transistor (T, T) that receives a variable voltage at its base. Application to signal folding circuits and to analog-to-digital converters using differential pairs of transistors.

Electronic network circuit with dissymmetrical differential pairs

Fast chainable carry look-ahead adder

A signal aliasing circuit that can be used especially to make a series interpolation cell of an interpolation analog-digital converter comprises two pairs of differential arms powered by one and the same current source connected to a first power supply terminal, each pair comprising two transistors, the transistors of one pair being parallel-connected with the transistors of the other pair. Each group of two parallel-connected transistors is connected by a respective common resistor to a second power supply terminal, the two outputs of the aliasing circuit being the combined collectors of the two groups of parallel-connected transistors. The disclosed device can be applied especially to converters whose architecture comprises what is known as a series interpolation part requiring high precision.

Aliasing circuit and series interpolation cell of an analog-digital converter using such a circuit

Signal-folding converters which establish two so-called fold analogue signals, whose curves of variation as a function of a voltage Vin to be converted cross over at multiple points. The architecture establishes n pairs of voltages varying with Vin and crossing over for regularly distributed values Vin&equals;V,. At least two current routing circuits are provided, each of which possesses at least three pairs of inputs and at least two outputs including a direct output and an inverse output. The direct outputs, linked together, provide a folded signal SR; the inverse outputs provide a complementary folded signal SRb. Each routing circuit receives three voltage pairs of rank k&minus;1, k, and k&plus;1 and includes a current source supplying a group of branches arranged as a tree-like structure. The apportioning of the current in each branchoff depends on the voltage pairs of rank k&minus;1, k, and k&plus;1, and the direct and inverse outputs of the circuit are tapped respectively from two different branches of the last stage of the tree-like structure.

Analog/digital converter with tree-structured folding circuit

Disclosed is an analog to digital converter with several cascade-connected interpolation and selection circuits. The function of an interpolation circuit is to produce five pairs of output signals from three pairs of input signals and select three pairs from among the five pairs to apply them to the next stage. Each pair comprises two interpolation signals that vary symmetrically and monotonically as a function of the voltage Vin, the signals of one pair being equal when the voltage Vin is equal to a reference voltage associated with this pair. There are five reference voltage associated with the five pairs. Among these five reference voltages, the three reference voltages (and therefore also the three corresponding pairs of signals) that most closely surround the input voltage Vin are selected. The reference voltages are increasingly closer together as the operation progresses in the succession of cascade-connected stages. The signals used to select the pairs of signals are used in a decoder that gives the bits of the analog-digital conversion.

Analog to digital converter using several cascade-connected

The invention concerns precision analogue-digital converters. For the fine conversion, supplying the low order bits (B0 to Bk) for an analogue voltage Vin to be converted, three ordinary differential amplifiers (ADA, ADB, ADC) are used connected to three voltage references VR(i-1), VR(i), VR(i+1). These three amplifiers supply differential output voltages (VAa, VAb, VBa, VBb, VCa, VCb) that vary as a function of Vin according to normal transfer functions for differential amplifiers. Intersection points of these various transfer curves are detected in interpolation circuits (firstly CIT1, then CIT2, etc). These intersection points are used as intermediate voltage references between the main references. Comparators (CMP0 . . . CMPk), placed at the output of interpolation circuits supply bits (B0 to Bk) indicating the value of Vin with respect to each of these intermediate references.

Analog digital converter

The disclosure relates to analog-digital converters. It is sought to limit the power consumption and obtain a better compromise among the different performance characteristics of the computer. In a general structure of a converter there are, firstly, a coarse converter for the most significant bits and, secondly, a fine converter for the least significant bits. One of them, generally, the fine converter, has differential amplifiers [AD(1) to AD(N)]receiving the voltage to be converted (Ve) and a reference voltage. It is proposed to place sample-and-hold circuits [EB(1) to EB(N)] at output of these differential amplifiers and to eliminate the sample-and-hold circuit that is often placed upline with respect to these amplifiers.

Growing community of inventors

Saint Egreve, France

Marc Wingender