Infineon Technologies Ag

Marc Ullmann

Georg Braun

Heinz H&ouml;nigschmid

Thomas Peter Haneder

Wolfgang Hönlein

Harald Bachhofer

The state of a ferroelectric transistor in a memory cell is read or stored, and the threshold voltage of further ferroelectric transistors in further memory cells in the memory matrix is increased during the reading or storing, or is increased permanently. A memory configuration including ferroelectric memory cells is also provided.

Memory configuration and method for reading a state from and storing a state in a ferroelectric transistor

An integrated memory has word lines that run in a first direction, and bit lines and control lines that run in a second direction, which is perpendicular to the first direction. A controllable path of each memory transistor connects one of the bit lines to one of the control lines. The control electrode of each memory transistor is connected to one of the word lines. Since the bit lines and control lines run in the same direction and are thus arranged parallel to one another, they can be arranged within a common wiring plane of the integrated memory. Since the terminals of the controllable path are usually likewise arranged in a common wiring plane, for example in a substrate of the integrated memory, it is possible, to arrange the bit lines and control lines in the same wiring plane as the controllable path of the transistors.

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Hamburg, Germany

Marc Ullmann