Lucent Technologies Inc.

At+t Corp.

At&t Ipm Corp.

Marc Stephen Diamondstein

Mohammad Shafiul Mobin

Mark Ernest Thierbach

David M Blaker

Homayoon Sam

Gregory S Ellard

Mohit Kishore Prasad

Jiancheng Mo

Hosahalli R Srinivas

Feng Chen

Gregory Stephen Ellard

A glitch-free clock switch circuit for an integrated circuit having a plurality of asynchronous clocks, wherein only one clock is selected at a time, and wherein the clock switching circuitry for switching from a currently selected clock to an inactive clock to next be selected is activated only for the time it takes to complete the switching. The clock switch circuit includes at least three sets of clock drivers, wherein each set is comprised of two drivers and separate clock drivers are each associated with the output clock, the currently selected clock and the clock to next be selected, respectively. An edge detector turns on these clock drivers in response to a clock select signal, and a set of synchronizers receive and synchronize the clock select signal first with the output clock and then with the currently selected clock and the clock to next be selected, respectively. A plurality of logic gates switches the clock output from the selected clock to the clock to next be selected by the clock select signal. A reset circuit turns off the clock drivers once the clock output has been switched from the selected clock to the clock to next be selected. The clock drivers for clocks that are not selected are turned off during and after the period of time the selected clock is switched to the clock to next be selected. Once the switching is complete, the entire clock switching circuit is turned off until another clock switching occurs.

Low power glitch-free clock switch

There is disclosed a loop counter reload circuit loads an initial count value into a counter and a shadow register. A count value output from the counter is changed by a predetermined displacement resulting in a changed count value. The count value from the shadow register is loaded into the counter if the changed count value has reached a predetermined reference value, and otherwise the changed count value is loaded into the counter.

Autoreload loop counter

In accordance with the present invention, a method and apparatus are provided for controlling an N-bit barrel shifter to shift the bits of an input word by a shift value. The method includes the steps of performing a ones' complement of an m-bit binary representation of a shift value to generate an input when the shift direction takes on a first direction and passing the binary representation of the shift value as the input when the shift direction takes on a second direction. Decoding the input into 2.sup.m control signals and generating a plurality of groups of control signals from the 2.sup.m control signals. Selecting one of the plurality of groups of control signals as the control activation for the barrel shifter. The apparatus provides bits of a binary representation of the shift value are passed through a plurality of exclusive OR gates and provided as inputs to a first decoder. The first decoder decodes the inputs into a plurality of bits used as control signals. The control signals are grouped in a plurality of groups. Some of the groups of control signals may be supplemented with additional control signals such as zero filling. Based on a select input a multiplexer selects which one of the plurality of groups of control signals is passed to control the barrel shifter. A second decoder decodes the shift direction and sign of the shift value to provide a select input to the multiplexer.

Fast conversion two's complement encoded shift value for a barrel shifter

There is an equalizer or a receiver including an equalizer which has means to factor detected symbols transmitted over a transmission channel into a magnitude portion and a repetitive phase portion. The receiver further has means to generate modified tap weights by multiplying the repetitive phase portion by tap weights representative of the channel. Modified tap weights are generated by multiplying the repetitive phase portion by tap weights representative of the channel. The modified tap weights are convolved with bits of possible states to generate possible transmitted symbols. A maximum likelihood sequence estimation is performed on the possible transmitted symbols comparing each possible transmitted symbol to a received symbol to generate an MLSE detected symbol. The detected symbol is multiplied by a rotating vector to generate a decoded symbol. In an alternate embodiment, a received symbol from the sequence of received symbols is multiplied by a rotating vector prior to performing the maximum likelihood sequence estimation.

MLSE before derotation and after derotation

In accordance with the present invention, a technique for efficiently utilizing memory in determining which next state accumulated cost to retain, such as in a communication system or a Viterbi decoder. The system includes a memory having a portion of registers allocated to a first array and a portion of registers allocated to a second array. The technique includes retrieving a present state accumulated cost from a storage register of the first array and calculating a next state accumulated cost based on the present state accumulated cost. The next state accumulated cost is stored in a storage register of the second array. The second array is designated as containing present state accumulated costs. A present state accumulated cost is retrieved from a storage register of the second array and used in calculating a subsequent next state accumulated cost. The subsequent next state accumulated cost is stored in a storage register of the first array.

Efficient utilization of present state/next state registers

An integrated circuit includes a digital signal processor (DSP) and an error correction co-processor (ECCP) that implements a Viterbi decoding function. The DSP and ECCP share a block of multi-port memory, typically by bus multiplexing a dual-port RAM. When the ECCP possesses the RAM, it inhibits the DSP from accessing that block of the RAM by asserting an EBUSY flag. This technique conserves and optimizes the RAM usage, allowing the DSP and ECCP to advantageously be formed on the same integrated circuit chip.

Growing community of inventors

Allentown, PA, United States of America

Marc Stephen Diamondstein