Teledyne E2v Semiconductors Sas

Marc Stackler

Rémi Laube

Jérôme Ligozat

Etienne Bouin

In an architecture for processing data comprising a control unit and converters CNto be synchronized to an active front of a common reference clock CLK, the synchronizing method makes provision for the converters to be arranged in at least one series chain, and for a procedure for synchronizing the converters by propagating a synchronizing signal SYNC-m emitted by the control unit, said signal being retransmitted as output OUT by each converter, after resynchronization to a clock active front, to a synchronization input IN of a following converter in the chain. Each converter comprises a synchronization configuration register REG containing at least one polarity parameter Sel-edgethat sets the polarity of the reference-clock front for reliable detection of a synchronizing signal received via the input of the converter. A phase parameter Sel-shiftfurthermore allows the phase of the sampling clocks of n converting cores of the converters, working at a sampling frequency obtained by dividing by n the CLK reference-clock frequency, to be synchronized.

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St Martin le Vinoux, France

Marc Stackler