International Business Machines Corporation

Marc Segre

Leon Lumelsky

Joe C St Clair

Alexander K Spencer

Robert L Mansfield

Satish Gupta

Moon Jung Kim

Jeffrey Alan Kusnitz

Andrew Paul Wyskida

Leslie Robert Wilson

James D Wagoner

John Anthony Moore

Hector G Romero, Jr

Paul Joseph Milot

Gary Bischoff

Jeffrey S Spencer

The present invention provides a method, system, and computer program product for prefetching sync data and for edge caching on a cellular device (e.g., a cell phone). The method for prefetching sync data comprises: providing unprocessed sync data at a first location; downloading the unprocessed sync data from the first location to a second location over a first network; processing the unprocessed sync data at the second location to provide preprocessed sync data; storing the preprocessed sync data in a cache; receiving a sync request from a mobile device; and immediately providing at least a portion of the preprocessed sync data stored in the cache to the mobile device.

Method, system, and computer program product for prefetching sync data and for edge caching sync data on a cellular device

A method for delivering data to a mobile device can begin with determination of the need to transmit data to a client application installed upon a mobile device by a provider in response to the occurrence of a predefined event. A session initiation protocol (SIP) message encapsulating the data can then be addressed to the mobile device using a static, unique identifier of the mobile device. The static, unique identifier can be acquired during registration of the mobile device for the service and can be electronically coupled with a hardware component of the mobile device. The SIP message can be conveyed to the Internet protocol (IP) multimedia subsystem (IMS) of an IP-based mobile communications network via a dedicated communications mechanism where it can be routed based on the static, unique identifier.

Resource-conserving technique for as-available data delivery to a mobile device

A system, method and computer-program product for a client device to securely access a private network through a public wireless network. The system establishes a first network tunnel between the client device and a gateway of the public wireless network and then authenticates the client device with an authentication server of the private network using the first tunnel. The authentication is proxied by an authentication server of the public network. Once the authentication is successful, a second tunnel is established between the client device and a gateway of the private network for secure access by the client device to the private network.

Secure access to a private network through a public wireless network

A single set of input devices (keyboard, mouse, etc.) is employed with a plurality of data processing systems each having a separate display. The logical display areas for the displays are arranged in a contiguous array to have common boundaries, with an edge (e.g., a right boundary or a lower boundary) of one logical display area coinciding with an edge of another logical display area (e.g., a left boundary or an upper boundary). When a cursor controlled by a pointing device is moved past a logical display area boundary which the current active data processing system shares in common with another data processing system, the active data processing system to which input device signals are transmitted is automatically switched to the other data processing system. No manual switching or hot-key sequence by the user is required, and the active data processing system may be automatically switch among any of a number of data processing systems simply by moving the cursor across logical display area boundaries between the data processing systems.

Automated keyboard mouse switch

A voice biometric authentication system and method. An authentication system is provided for authenticating a user of a telephonic device, comprising: a setup system for capturing and storing an authentic user voice sample; a comparison system that compares the authentic user voice sample with an inputted voice sample and generates a comparison result; and a control system for controlling access to the telephonic device, wherein the control system: analyzes the comparison result for an initial inputted voice sample received when a telephone call is initiated; and periodically analyzes comparison results for ongoing inputted voice samples received during the telephone call.

System and method for telephonic voice authentication

A method and apparatus for enabling existing application programs for operation in speech recognition environments. Existing applications programs written with a dynamically linked library or object library, with no speech recognition capability, are capable of accepting input from a speech recognition without modification. An alternate dynamic library or object library is provided that supports the same interface or objects used by the original program. The alternate library is written so that it is aware of and receives input from the speech recognition system. The alternate library passes the input to the application program using the existing interfaces.

Adding speech recognition libraries to an existing program at runtime

Data transfers between a workstation bus and a graphics adapter bus are handled by a plurality of first-in-first-out (FIFO) buffers, each of which is independently operable to transfer data in a selected direction between the two buses. The FIFOs are accessible either directly by the workstation processor or by means of a DMA operation. Each FIFO is assigned a unique range of addresses in the address space of the workstation processor to permit a workstation process to transfer a block of data to or from a selected FIFO using a single instruction. Workstation writes (reads) to a FIFO are suspended in response to a first status signal indicating that the high (low) threshold for that FIFO has been reached and are restarted in response to a second status signal indicating that the low (high) threshold has been reached. A buffer counter indicating the amount of data in each FIFO is initialized at zero for outbound transfers from the workstation to the adapter or at the maximum buffer count for inbound transfers from the adapter to the workstation. The buffer count is incremented in response to accesses from the workstation side and is decremented in response to accesses from the adapter side, regardless of the direction of transfer.

Bidirectional FIFO buffer for interfacing between two buses of a

A frame buffer memory organization which is capable of accessing a pixel aligned M by N array of contiguous pixels on the screen from a frame buffer memory constructed of an M by N array of memory chips by driving a common address bus to all the memory chips, and by driving N RAS wires horizontally across the memory chip array and M CAS wires vertically down the memory chip array. The writing of individual pixels in this array is enabled by energizing the write enable pins to each memory chip directly. The data wires in the memory organization are tied together such that M horizontal pixels in a single row can be read or written simultaneously. Additionally, all M and N pixels may be written simultaneously if the data in all vertical columns is the same. The frame buffer includes a selectively energizable plane mask for disabling desired planes of accessed pixels. By sequentially controlling the output enables to the different rows of the addressed M by N array, the frame buffer can provide rapid access to N-1 rows after normally accessing the first one. The described architecture will work equally well for M by N other array organizations with a different size (e.g., 8 by 8, 3 by 4, 5 by 4, etc). These other configurations would of course require as many concurrently accessable memory chips or sections as there are pixels in the accessed rectangular array as will be well understood.

Frame buffer architecture capable of accessing a pixel aligned M by N

A display adapter for displaying graphics data in pixel form on a high resolution display monitor includes a digital signal processor for managing adapter resources and controlling coordinate transformations, a system storage which is divided into a first portion for storing instructions for the digital signal processor and the second portion for storing data representing information to be displayed, an input buffer for permitting asynchronous and overlapped communication between the graphics display adapter and a host computer to speed operation of the system, a pixel processor for drawing vectors and manipulating areas to be displayed on the monitor, a bit mapped frame buffer, a color palette connected to outputs of the frame buffer for providing appropriate color signals to the high resolution monitor and a cursor circuit for controlling display of a cursor on the screen on the monitor.

High resolution graphics display adapter

A multichannel data path architecture which assists a host processor in communication with the frame buffer in order to increase the overall system performance. The architecture provides automatic frame buffer data path rearrangement depending on the pixel address and the host data interpretation. It utilizes a minimum of shift registers, accumulators and control circuitry to provide the requisite storage, reconfiguration and frame buffer access functions. The architecture extends bit-blt (bit block transfer) conventional operations in order to provide high quality 'antialiased' text and graphics directly in the architecture without requiring the calculation of colors by the host processor. Finally, it assists the 'burst' mode update of an arbitrary single plane of a frame buffer, which is especially important when high denisty chips are used for the frame buffer implemenation.

Pixel data path for high performance raster displays with

A graphics display system including a circuit that receives graphics information to be displayed and a memory that stores the graphics information in a memory array that includes a portion that directly corresponds to the image area for display. The memory provides a single access operation to the array during a single memory cycle. Circuitry is provided that is connected to the receiving means and to the memory that provides graphics information to an N by M portion of the memory array during a single memory cycle (wherein N and M are integers each greater than one). A display is connected to the memory that displays the graphics information contained in the image area array portion of the memory. The graphics display system further includes the capability to provide a patterned line intersection where the continuity of the line pattern is maintained along the intersection of the lines.

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Raleigh, NC, United States of America

Marc Segre