Imec Vzw

Interuniversitair Microelektronica Centrum (imec)

Other

Applied Materials, Inc.

Imec

Marc Schaekers

Antony Premkumar Peter

Serge Vanhaelemeersch

Boon Teik Chan

Paul Mertens

Karen Irma Maex

Ricardo Alves Donaton

Marc Marcel Heyns

Zheng Tao

Liesbeth Witters

Hessel Sprey

Silvia Armini

Ann Witvrouw

Zsolt Tokei

Steven Demuynck

Sven Van Elshocht

Herbert Struyf

Brenda Eyckens

Michael Baklanov

Karine Kenis

Laure Elisa Carbonell

Michael McGeary

Maria Gromova

Karen A Maex

Michael R Baklanov

Ricardo Donaton

A method for fabricating a semiconductor structure is provided. The method includes providing a patterned substrate comprising a semiconductor region and a dielectric region. A conformal layer of a first dielectric material is deposited directly on the patterned substrate. A layer of a sacrificial material is deposited overlying the conformal layer of the first dielectric material. The sacrificial material is patterned, whereby a part of the semiconductor region remains covered by the patterned sacrificial material. A layer of a second dielectric material is deposited on the patterned substrate, thereby completely covering the patterned sacrificial material. A recess is formed in the second dielectric material by completely removing the patterned sacrificial material. The exposed conformal layer of the first dielectric material is removed selectively to the semiconductor region.

Method for forming a field effect transistor device having an electrical contact

Method for forming an interconnect structure, comprising the steps of: forming a recessed structure in a dielectric material on a substrate; at least partially filling said recessed structure with a metal chosen from the group consisting of copper, nickel and cobalt; introducing the substrate in a CVD reactor; bringing the substrate in the CVD reactor to a soak temperature and subsequently performing a soak treatment by supplying a germanium precursor gas to the CVD reactor at the soak temperature, thereby substantially completely converting the metal in the recessed structure to a germanide.

Method for manufacturing germamde interconnect structures and corresponding interconnect structures

A method for forming an electrical contact to a semiconductor structure is provided. The method includes providing a semiconductor structure, providing a metal on an area of said semiconductor structure, wherein said area exposes a semiconductor material and is at least a part of a contact region, converting said metal to a Si-comprising or a Ge-comprising alloy, thereby forming said electrical contact on said area, wherein said converting is done by performing a vapor-solid reaction, whereby said semiconductor structure including said metal is subjected to a silicon-comprising precursor gas or a germanium-comprising precursor gas.

Method for forming an electrical contact

A method of depositing a structural SiGe layer is presented. The structural SiGe layer may be located on top of a sacrificial layer above a substrate. The substrate may contain a semiconductor device such as a CMOS electronic circuit. The presented method uses a silicon source and a germanium source in a reaction zone to grow the structural SiGe layer. Hydrogen is introduced into the reaction zone and it may be used to dilute the silicon source and the germanium source. The resultant reaction occurs at temperatures below 450 degrees C., thereby preventing degradation of electronic device and/or other devices/materials located in the substrate.

Method of producing microcystalline silicon germanium suitable for micromachining

A method for anisotropic plasma etching of organic-containing insulating layers is disclosed. According to this method at least one opening is created in an organic-containing insulating layer formed on a substrate. These openings are created substantially without depositing etch residues by plasma etching said insulating layer in a reaction chamber containing a gaseous mixture which is composed such that the plasma etching is highly anisotropic. Examples of such gaseous mixtures are a gaseous mixture comprising a fluorine-containing gas and an inert gas, or a gaseous mixture comprising an oxygen-containing gas and an inert gas, or a gaseous mixture comprising HBr and an additive. The plasma etching of the organic-containing insulating layer can be performed using a patterned bilayer as an etch mask, said bilayer comprising a hard mask layer, being formed on said organic-containing insulating layer, and a resist layer being formed on said hard mask layer. A method is disclosed for forming a layer, protecting exposed surfaces of low-k dielectrics. More particularly the method comprises the steps of sealing exposed surfaces of a, preferably porous, low-k dielectric, by forming a protective layer on exposed surfaces during or after the step of patterning openings in the porous dielectric layers. Preferably this protective layer is formed by a N2/O2 plasma treatment of the exposed surfaces.

Anisotropic etching of organic-containing insulating layers

A method of growing a silicon oxide layer on a silicon substrate by means of a thermal oxidation in a furnace in the presence of a gaseous mixture, said mixture comprising oxygen and Cl , said Cl being generated by an organic chlorine-carbon source, particularly oxalyl chloride. This method is directed to the growth of (ultra) thin silicon oxides and/or the cleaning of a substrate using a low oxidation power. Consequently the method disclosed is especially suited for temperature below &deg; C. and for oxidation ambients containing only small amounts of oxygen.

Method for growing thin silicon oxides on a silicon substrate using chlorine precursors

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Leuven, Belgium

Marc Schaekers