Micron Technology Incorporated

Marc S Hamilton

Kevin Roy Brandt

Kishore Kumar Muchherla

Sampath K Ratnam

Daniel J Hubbard

Christopher S Hale

Peter Sean Feeley

Ashutosh Malshe

Yun Li

Preston Allen Thomson

Scott Anthony Stoller

William Richard Akin

Suresh Rajgopal

A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.

Memory device with dynamic cache management

A processing device in a memory system detects a data loss occurrence in a block of a memory component. The processing device further designates the block as a quarantined block, performs a stress test on the block, and depending on whether the stress test on the block satisfies a testing criterion, either designates the block as usable by the memory component or retires the block of the memory component.

Managing block retirement for temporary operational conditions

One or more requests are received from a host system while a media management scan is in progress on a memory component in a memory sub-system. The media management scan in progress is suspended. The request received from the host system are serviced. Once the host system is serviced, the media management scan is resumed on the memory component.

Handling of host-initiated requests in memory sub-systems

A memory component includes multiple fuses, a memory array having a multiple blocks, and control logic operatively coupled with the memory array and the plurality of fuses. The control logic is to perform operations including detecting a failure to completely erase a block of the plurality of blocks in response to an attempted erasure of the block; receiving a blow fuse command in response to the failure to completely erase the block; and blowing a fuse, of the plurality of fuses, coupled with the block, to make the block electrically inaccessible to the control logic in response to receipt of the blow fuse command.

Handling bad blocks generated during a block erase operation

A processing device in a memory system detects a data loss occurrence in a block of a memory component. The processing device identifies a behavioral criterion associated with the data loss occurrence in the block of the memory component. The processing device further increments a counter associated with the block in response to an occurrence of the behavioral criterion, wherein a value of the counter corresponds to a number of occurrences of a plurality of behavioral criteria associated with data loss occurrences in the block. Responsive to determining that the value of the counter satisfies a first threshold criterion, the processing device designates the block as a quarantined block, performs a stress test of a plurality of stress tests of the block, and responsive to the block failing a first stress test, the processing device retires the block of the memory component.

A memory component includes multiple fuses, a memory array having a multiple blocks, and control logic operatively coupled with the memory array and the plurality of fuses. The control logic is to receive an erase command associated with the memory array and attempt to erase, in response to receipt of the erase command, a block of the multiple blocks from the memory array. The control logic is further to detect a failure to completely erase the block. The control logic is further to receive a blow fuse command in response to the failure to completely erase the block. The control logic is to blow a fuse, of the multiple fuses, which is coupled with the block, to make the block of the multiple blocks inaccessible to the control logic.

A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: select a garbage collection (GC) source block storing valid data, and designate a storage mode for an available memory block based on the valid data, wherein the storage mode is for configuring memory cells in the available memory block as cache memory that stores a number of bits less than maximum storage capacities thereof for subsequent or upcoming data writes.

A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: select a garbage collection (GC) source block storing valid data, calculate a valid data measure for the GC source block for representing an amount of the valid data within the GC source block, and designate a storage mode for an available memory block based on the valid data measure, wherein the storage mode is for controlling a number of bits stored per each of the memory cells for subsequent or upcoming data writes.

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Eagle City, ID, United States of America

Marc S Hamilton