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Centre National De La Recherche Scientifique

Commissariat a L'energie Atomique

France Telecom

Institut National Polytechnique De Grenoble

Marc Renaudin

Pascal Vivet

Patrice Senn

Edith Beigne

Jacky Bouvier

Gilles Privat

Yassine Rjimati

Christophe Scarabello

David Nguyen Van Mau

Ghislain Bouesse

Boubkar Boulahia

Jérôme Quartana

Alain Fonkoua

Patricia Planet

Bertrand Folco

Yannick Monnet

Andr&eacute; Adrial

Yanick Monnet

The electronic circuit comprises a logic module performing a first function. A number generator generates a series of first numbers. A voltage generator supplies the logic module with a first minimum operating voltage of the logic module and a variable additional second voltage having electrical characteristics that are functions at least of the first series of first numbers. The variable additional second voltage comprises at least a fixed voltage defined by an offset voltage value and a first periodic voltage defined at least by a first frequency and a first amplitude. The voltage generator is configured so that the value of the offset voltage, of the first frequency and/or of the first amplitude are defined at least from the series of first numbers.

Electronic circuit secured by disruption of its power supply

The integrated circuit includes a functional block performing a logic and/or analog function. A control circuit is configured to transmit at least a first signal to the receiver and receive a second signal from receiver. The electrically conducting lines' first and second series connect the control circuit and receiver to perform the first and second signals' transit. A plurality of monitoring stations is simultaneously connected to first and second series of electrically conducting lines to define a first elementary electric pattern in the electrically conducting lines' first series and a distinct second elementary electric pattern equivalent to first elementary electric pattern in the electrically conducting lines' second series. A shield at least partially covers the functional block. The control circuit is configured to detect modification of first elementary electric pattern with respect to the second elementary electric pattern by absence of receipt of the second signal after a predefined time-out.

Protected integrated circuit

The asynchronous circuit includes an input channel, a divergence operator connecting the input channel to a plurality of intermediate channels, a convergence operator gathering the intermediate channels into a single output channel, a main sequencer including a plurality of sequentially-activated control channels, each intermediate channel being associated to a control channel, and a switch arranged in a request path of one of the intermediate channels and connected to the last active control channel. The circuit further includes a memory circuit, arranged in each of the other intermediate channels, connected to the associated control channel and configured to transmit the request signal of the associated intermediate channel to the output channel and to modify an output state of the associated intermediate channel, by means of the main sequencer, without requiring any state change of the input channel.

Asynchronous circuit with sequential write operations

The asynchronous circuit includes a fork having at least two branches, each branch being connected to a logic gate so that the logic gate receives as input a branch-ending signal. It further includes a circuit for branching the branch-ending signal at the level of each logic gate to form a branched signal, and a blocking circuit comprising a Muller gate and receiving as input at least one branched signal, the blocking circuit being configured to prevent the propagation of an output signal when the branch-ending signals are in different logic states.

Delay-insensitive asynchronous circuit

The asynchronous circuit insensitive to delays comprises at least one time delay insertion circuit on the propagation path of a signal. The delay insertion circuit comprises, between an input and an output of the signal, a Muller C-element and a plurality of delay circuits connected in series to an output of the Muller C-element. The outputs of the delay circuits are connected to corresponding inputs of a multiplexing circuit having an output constituting the output of the delay insertion circuit. The Muller C-element comprises an input connected to the output of the last delay circuit via an inverter gate, and an input constituting the input of the signal to the delay insertion circuit. The multiplexing circuit control circuit preferably comprises a random generator.

Asynchronous circuit insensitive to delays with time delay insertion circuit

A network and a data transmission method between elements in such a network using an asynchronous communication protocol of the 'send/accept' type. At least one node in the network operations without an internal clock, this node determining a transfer hierarchy between two data packets to be routed to the same output, at least as a function of a priority channel information associated with each data packet.

Communication node architecture in a globally asynchronous network on chip system

A micro-electronic component for a portable object is of the type which incorporates digital processing means, and an interface for contact-free electromagnetic coupling with a remote station. The digital processing means can operate according to an operating mode of the request/acknowledgement type, which is substantially insensitive to the propagation time, without a global, regular clock. The component additionally comprises adapter means, which can adapt the signals of the contact-free interface to the signals of the digital processing means and vice versa, in order to permit two-way dialogue with the remote station.

Micro-electronic component, incorporating asynchronous digital processing means and a contact-free electromagnetic coupling interface

Improved process for parallel operation of several computation units, especially in image processing, and corresponding architecture. Several computation units which are together intended to evaluate in an iterative and cellular manner the convergence values of a plurality of variables associated respectively with the various points of a predetermined grid each variable having to satisfy a prespecified iterative relation between itself and n neighbouring variables associated with n neighbouring grid points (P2-P5), a memory means is assigned per point of the grid, intended to store successively all the values of the variable associated with this grid point, the computation units are apportioned in such a way as to assign every grid point to a computation unit and two distinct computation units to two chosen neighbouring points of the grid, all the computation units are made to operate in parallel and independently of one another, and for each current point of the grid, the computation unit assigned to this current point is made to compute each successive value of the variable associated with this current point on the basis of the value contained in the memory means assigned to the current point and of those available and arising from the memory means assigned to the points neighbouring the current point, irrespective of the iteration levels to which these available values correspond, and the said computation unit is made to store each new value thus computed in the memory means associated with the current point.

Process for parallel operation of several computation units, especially

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Biviers, France

Marc Renaudin