Sun Microsystems, Inc.

Oracle America, Inc.

Immersion Corporation

Virtual Technologies, Inc.

Microsystems, Inc.

Sun Microsysytems, Inc.

Marc R Tremblay

Shailender Chaudhry

James Michael O'Connor

William N Joy

Quinn Able Jacobson

Paul Caprioli

Gary R Lauterbach

Joseph I Chamdani

Sanjay Vishin

Michael Frank Deering

Subramania Sudharsanan

Jeffrey Meng Wah Chan

Mark S Moir

James F Kramer

Ole Agesen

Mark H Yim

Graham Ricketson Murphy

Anup S Tirumala

Jeffrey Meng Chan

Guy Lewis Steele, Jr

Maurice P Herlihy

Steven K Heller

Sherman H Yip

Andre Kowalczyk

Derek R White

Christopher J Ullrich

Mario I Wolczko

Robert Yung

Sharada Yeluri

Scott R Nelson

Daniel H Gomez

Chandramouli Banerjee

William R Bush

Frank C Chiu

Ron Carmel

Hugo J C DesRosiers

Jerry Tian

Gary S Goldman

Dale Robert Greenley

Michael R Allen

Bruce E Petrick

Guy L Steele

Nik Shaylor

Shrinath A Keskar

Michael Denis O'Connor

Steve Heller

Gary R Oblock

Anup S Tirumula

Biyu Pan

Bi-Yu Pan

Jeffrey M W Chan

Krishna C Yarlagadda

A computer processor pipeline has both an architectural register file and a working register file. The lifetime of an entry in the working register file is determined by a predetermined number of instructions passing through a specified stage in the pipeline after the location in the working register file is allocated for an instruction. The size of the working register file is selected based upon performance characteristics. A working register file creditor indicator is coupled to the front end pipeline portion and to the back end pipeline portion. The working register file credit indicator is monitored to prevent a working register file overflow. When the a location in the architectural register file is read early, the location is monitored to determine whether the location is written to prior to issuance of the instruction associated with the early read.

Mechanism for increasing the effective capacity of the working register file

A register file, in a processor, includes a first plurality of registers of a first size, n-bits. A decoder uses a mapping that divides the register file into a second plurality M of registers having a second size. Each of the registers having the second size is assigned a different name in a continuous name space. Each register of the second size includes a plurality N of registers of the first size, n-bits. Each register in the plurality N of registers is assigned the same name as the register of the second size that includes that plurality. State information is maintained in the register file for each n-bit register. The dependence of an instruction on other instructions is detected through the continuous name space. The state information allows the processor to determine when the information in any portion, or all, of a register is valid.

Method and structure for solving the evil-twin problem

A processor includes a device providing a throttling power output signal. The throttling power output signal is used to determine when to logically throttle the power consumed by the processor. At least one core in the processor includes a pipeline having a decode pipe; and a logical power throttling unit coupled to the device to receive the output signal, and coupled to the decode pipe. Following the logical power throttling unit receiving the power throttling output signal satisfying a predetermined criterion, the logical power throttling unit causes the decode pipe to reduce an average number of instructions decoded per processor cycle without physically changing the processor cycle or any processor supply voltages.

Logical power throttling of instruction decode rate for successive time periods

One embodiment of the present invention provides a processor that supports multiple-issue execution. This processor includes a register file, which contains an array of memory cells, wherein the memory cells contain bits for architectural registers of the processor. The register file also includes multiple read ports and multiple write ports to support multiple-issue execution. During operation, if multiple read ports simultaneously read from a given register, the register file is configured to: read each bit of the given register out of the array of memory cells through a single bitline associated with the bit; and to use a driver located outside of the array of memory cells to drive the bit to the multiple read ports. In this way, each memory cell only has to drive a single bitline (instead of multiple bitlines) during a multiple-port read operation, thereby allowing memory cells to use smaller and more power-efficient drivers for read operations.

Processor with a register file that supports multiple-issue execution

A man-machine interface which provides tactile feedback to various sensing body parts is disclosed. The device employs one or more vibrotactile units, where each unit comprises a mass and a mass-moving actuator. As the mass is accelerated by the mass-moving actuator, the entire vibrotactile unit vibrates. Thus, the vibrotactile unit transmits a vibratory stimulus to the sensing body part to which it is affixed. The vibrotactile unit may be used in conjunction with a spatial placement sensing device which measures the spatial placement of a measured body part. A computing device uses the spatial placement of the measured body part to determine the desired vibratory stimulus to be provided by the vibrotactile unit. In this manner, the computing device may control the level of vibratory feedback perceived by the corresponding sensing body part in response to the motion of the measured body part. The sensing body part and the measured body part may be separate or the same body part.

Tactile feedback man-machine interface device

Embodiments of the present invention provide a system that executes a transaction on a simultaneous speculative threading (SST) processor. In these embodiments, the processor includes a primary strand and a subordinate strand. Upon encountering a transaction with the primary strand while executing instructions non-transactionally, the processor checkpoints the primary strand and executes the transaction with the primary strand while continuing to non-transactionally execute deferred instructions with the subordinate strand. When the subordinate strand non-transactionally accesses a cache line during the transaction, the processor updates a record for the cache line to indicate the first strand ID. When the primary strand transactionally accesses a cache line during the transaction, the processor updates a record for the cache line to indicate a second strand ID.

Facilitating transactional execution in a processor that supports simultaneous speculative threading

Reducing temperature and power by instruction throttling at decode stage of processor pipeline in time constant duration steps

One embodiment of the present invention provides a system that merges checkpoints on a processor. The system starts by executing instructions speculatively during a speculative-execution episode. The system then generates a first checkpoint and a second checkpoint during the speculative-execution episode. Next, the system merges the first checkpoint with the second checkpoint during the speculative-execution episode, wherein merging the first and second checkpoints conserves processor resources.

Merging checkpoints in an execute-ahead processor

One embodiment of the present invention provides a system that synchronizes threads on a multi-threaded processor. The system starts by executing instructions from a multi-threaded program using a first thread and a second thread. When the first thread reaches a predetermined location in the multi-threaded program, the first thread executes a Start-Transactional-Execution (STE) instruction to commence transactional execution, wherein the STE instruction specifies a location to branch to if transactional execution fails. During the subsequent transactional execution, the first thread accesses a mailbox location in memory (which is also accessible by the second thread) and then executes instructions that cause the first thread to wait. When the second thread reaches a second predetermined location in the multi-threaded program, the second thread signals the first thread by accessing the mailbox location, which causes the transactional execution of the first thread to fail, thereby causing the first thread to resume non-transactional execution from the location specified in the STE instruction. In this way, the second thread can signal to the first thread without the first thread having to poll a shared variable.

Method and apparatus for synchronizing threads on a processor that supports transactional memory

One embodiment of the present invention provides a system that selectively monitors load instructions to support transactional execution of a process, wherein changes made during the transactional execution are not committed to the architectural state of a processor until the transactional execution successfully completes. Upon encountering a load instruction during transactional execution of a block of instructions, the system determines whether the load instruction is a monitored load instruction or an unmonitored load instruction. If the load instruction is a monitored load instruction, the system performs the load operation, and load-marks a cache line associated with the load instruction to facilitate subsequent detection of an interfering data access to the cache line from another process. If the load instruction is an unmonitored load instruction, the system performs the load operation without load-marking the cache line.

Selectively monitoring loads to support transactional program execution

A system that facilitates improving performance of a processor during scout mode. During a normal-execution mode, the system executes instructions for using main thread. Upon encountering a stall condition during execution of the main thread, the system generates a checkpoint. The system then enters a scout mode, wherein instructions are speculatively executed by a speculative thread to prefetch future memory references, but results are not committed to the architectural state of the processor. Upon encountering a memory reference during scout mode, the system issues a prefetch for the memory reference. If the stall condition that caused the processor to enter scout mode is resolved, the system uses the checkpoint to resume execution of the main thread from the instruction that caused the stall condition, and simultaneously continues executing instructions in scout mode using the speculative thread from the point where the speculative thread left off.

Continuing execution in scout mode while a main thread resumes normal execution

A technique recovers return address stack (RAS) content and restores alignment of a RAS top-of-stack (TOS) pointer for occurrences of mispredictions due to speculative operation, out-of-order instruction processing, and exception handling. In at least one embodiment of the invention, an apparatus includes a speculative execution processor pipeline, a first structure for maintaining return addresses relative to instruction flow at a first stage of the pipeline, at least a second structure for maintaining return addresses relative to instruction flow at a second stage of the pipeline. The second stage of the pipeline is deeper in the pipeline than the first stage. The apparatus includes circuitry operable to reproduce at least return addresses from the second structure to the first structure.

Return address stack recovery in a speculative execution computing apparatus

By encoding an exception triggering value in storage referenced by an instruction in an otherwise unused slot (e.g., the delay slot of a delayed control transfer instruction or an unused instruction position in a VLIW-based architecture) coinciding with a safe point, an efficient coordination mechanism can be provided for multi-threaded code. Because the mechanism(s) impose negligible overhead when not employed and can be engaged in response to an event (e.g., a start garbage collection event), safe points can be defined at call, return and/or backward branch points throughout mutator code to reduce the latency between the event and suspension of all threads. Though particularly advantageous for thread suspension to perform garbage collection at safe points, the techniques described herein are more generally applicable to program suspension at coordination points coinciding with calls, returns, branches or calls, returns and branches therein.

Cooperative preemption mechanism for garbage-collected multi-threaded computation

One embodiment of the present invention provides a system that selectively monitors store instructions to support transactional execution of a process, wherein changes made during the transactional execution are not committed to the architectural state of a processor until the transactional execution successfully completes. Upon encountering a store instruction during transactional execution of a block of instructions, the system determines whether the store instruction is a monitored store instruction or an unmonitored store instruction. If the store instruction is a monitored store instruction, the system performs the store operation, and store-marks a cache line associated with the store instruction to facilitate subsequent detection of an interfering data access to the cache line from another process. If the store instruction is an unmonitored store instruction, the system performs the store operation without store-marking the cache line.

Selectively monitoring stores to support transactional program execution

Growing community of inventors

Mountain View, CA, United States of America

Marc R Tremblay