Silicon Graphics, Incorporated

Other

Marc R Hannah

Michael B Nagy

The present disclosure relates to methods and systems to manage traffic density in a transportation system, and by doing so, maintain, in one embodiment, traffic flows near optimum levels to maximize road capacity and minimize travel times. The method includes, in one embodiment, a mechanism for vehicles to request road access from a centralized control, a queuing system that allows road access to be granted to individual vehicles over an extended period of time in a fair and organized fashion, a measurement system that allows traffic flow and density throughout the system to be determined in real-time, and an enforcement and fraud prevention mechanism to ensure that the rules and permissions imposed by the system are followed.

Managed access system for traffic flow optimization

A circuit for translating pixel data to be displayed on the output display of a computer system including a plurality of color index maps for providing a first set of digital values of shades to produce a final color on an output display in response to color index values; and a plurality of gamma correction maps for providing a second set of digital values of shades to produce a final color on an output display in response to the first set of digital values of shades.

Integrated apparatus for displaying a plurality of modes of color

In a computer graphics system, a semiconductor chip used in performing texture mapping. Textures are input to the semiconductor chip. These textures are stored in a main memory. Cache memory is used to accelerate the reading and writing of texels. A memory controller controls the data transfers between the main memory and the cache memory. Also included within the same semiconductor chip is an interpolator. The interpolator produces an output texel by interpolating from textures stored in memory. The interpolated texel value is output by the semiconductor chip, thereby minimizing transmission bandwidth as well as redundant storage of texture maps in a multi-processor environment.

Apparatus and method for integrating texture memory and interpolation

The present invention relates to the generation of display identification (ID) information in a computer display system. The display ID generator includes a memory which stores display ID information. A control logic device couples the information from the memory to a first FIFO. A state machine accesses the information held in the first FIFO and determines the duration information. Next, the state machine couples the information to a second FIFO. Last, the information in the second FIFO is coupled to a third memory and a sequential counter. After initial loading of information in second memory and sequential counter, the sequential counter determines when second memory and itself will be loaded with the next set of information. Once the sequential counter reaches zero, it generates a signal enabling itself and the second memory to load the next set of information.

Method and apparatus for generating display identification information

An apparatus and a method of generating video timing information and display ID information wherein the video timing generator includes a memory, typically a random access memory, which stores video timing information. A control logic device couples the information from memory to a FIFO. The control device further couples the initial information from the FIFO to a second memory, typically a register, and a sequential counter. After initial loading of information in the second memory and sequential counter, the sequential counter determines when the second memory and itself will be loaded with the next set of information. Once the sequential counter reaches zero, it generates a signal enabling itself and the second memory to load the next set of information. The display ID generator includes a memory which stores display ID information. A control logic device couples the information from the memory to a first FIFO. A state machine accesses the information held in the first FIFO and determines the duration information. Next, the state machine couples the information to a second FIFO. Last, the information in the second FIFO is coupled to a third memory and a sequential counter. After initial loading of information in second memory and sequential counter, the sequential counter determines when second memory and itself will be loaded with the next set of information. Once the sequential counter reaches zero, it generates a signal enabling itself and the second memory to load the next set of information.

Video timing and display ID generator

A cursor generator for use in a computer system having a high pixel clock rate. The cursor generator includes a first memory which stores a line of the cursor for display on the display device and a second memory which stores the entire cursor. The data for the line of the cursor can be more quickly retrieved from the first memory than from the second memory, and the first memory is clocked under the control of the high pixel clock rate while the second memory is clocked at a slower clock rate. A controller couples data for the one line of the cursor from the second memory, which is typically dynamic random access memory to the first memory which is typically a high speed register or a combination of registers and multiplexors. The controller couples the data for one line at a time of the cursor to the display device in order to display the cursor in conjunction with the rest of time image displayed on the display device.

High speed cursor generation apparatus

A graphics processor is coupled to a plurality of RAMs (Random Access Memories) for storing a frame of a display. The processor provides a separate RAS (Row Address Strobe) signal and a separate CAS (Column Address Strobe) signal to each of the memories so that row and/or column addresses to each of the RAMs can be latched using a staggered timing sequence. Data can be written into or read from memory using this staggering technique, wherein overall data transfer rate is faster than the memory cycle time of each to of the RAMs.

Graphics processor with staggered memory timing

A method and apparatus for clearing a Z-buffer in a raster scanned, computer controlled video display system having a frame buffer and a Z-buffer is disclosed. The method includes the step of writing a plurality of bits into pixel locations of the frame buffer, which pixel locations will be cleared in the Z-buffer and on the screen of the video display. Those plurality of bits invalidating the Z values in the Z-buffer corresponding to those pixel locations.

Method and apparatus for clearing a region of Z-buffer

A graphics processor is coupled to a plurality of RAMs (Random Access Memories) for storing a frame of a display. The processor provides a separate RAS (Row Address Strobe) signal and a separate CAS (Column Address Strobe) signal to each of the memories so that row and/or column addresses to each of the RAMs can be latched using a staggered timing sequence. Data can be written into or read from memory using this staggering technique, wherein overall data transfer rate is faster than the memory cycle time of each of the RAMs.

A method for updating a single ported, pipelined Z-buffer where the Z-buffer is updated only after determining the beginning and ending location of a continuous group of pixel locations requiring updating in the Z-buffer.

Method for updating pipelined, single port Z-buffer by segments on a

A system for processing of data wherein the data is inputted over time into the system such that a second packet of data is inputted before a first packet of data, the system comprising a first processor coupled to a second processor, the first processor operating on only the first packet of data and the second processor operating on only the second packet of data.

Interleaved pipeline parallel processing architecture

An improvement for providing color information in a raster scanned video display apparatus where color data is stored in a frame buffer for each pixel in addition to color data. The color data is coupled to a crossbar switch to provide several sets of color data at the output of the switch. A multiplexer receives these several sets of color information and selects between them based on the color mode data. This permits the same color code to represent more than a single color. In a display, color in windows may then be generated from different programs, eliminating color-code dependencies between programs.

Pixel mapping apparatus for color graphics display

YA dual clock shift register for use in a computer display system for converting a higher resolution image for a computer screen to a lower resolution image for display on a lower resolution display apparatus. The dual clock shift register includes a first shift register which is used to apportion a second shift register between control by two different clock rates.

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Los Altos, CA, United States of America

Marc R Hannah