Globespan Virata Corporation

Globespan, Inc.

Marc R Delvaux

Ronen Habot

Daniel Amrany

William H Scholtz

Wenwei Pan

Jian Wang

Richard Gut

Mazhar Alidina

A memory optimized system and method for data interleaving/de-interleaving are disclosed. A data interleaver/de-interleaver may be implemented with a memory device and an improved data interleaver/de-interleaver. The improved data interleaver/de-interleaver may be implemented with a controller, a first array, and a second array. The first array identifies a maximum depth value for each of a plurality of memory segments responsive to both a block data length and the desired interleaving/de-interleaving depth. The second array comprises an index associated with each of the plurality of memory segments that may be used to derive write and read addresses. In its broadest terms, the method can be described as: identifying a block data length, N, and an interleaver/de-interleaver depth, D; initializing a set of pointers associated with each of N memory segments; initializing a set of pointer maximum values responsive to the relative magnitude of N and D, identifying a memory index responsive to a base address and the set of pointer maximum values; using a memory segment identifier, a word identifier, and a byte identifier along with the memory index and the pointers to write/read the bytes of code words.

System and method for efficient convolutional interleaving/de-interleaving

A system and method for performing a general ternary branch instruction is provided. Additionally, different approaches are provided for reducing the complexity of a ternary branch instruction word and corresponding hardware.

Jumping to a recombine target address which is encoded in a ternary branch instruction

A multi-channel communication link generates a transport data protocol unit (TPDU) corresponding to each data packet received at a particular interface in a packet switching network. Each TPDU may comprise a data packet in accordance with a standard data transfer protocol and a modified header comprising a sequence number responsive to the relative position of the data packet within a data stream. The multi-channel communication link may inverse multiplex the various TPDUs for transmission across a plurality of asynchronous communication lines. A multi-channel communication link in accordance with the present disclosure may comprise a source first-in first-out (FIFO) buffer, a source line multiplexer/demultiplexer, a plurality of asynchronous communication links, a destination line multiplexer/demultiplexer, and a destination FIFO buffer. The present disclosure also provides a method for transferring data between computing devices via a virtual transport link.

System and method for combining multiple physical layer transport links

A data bus address extender is presented. The data bus extender may be deployed in cooperation with a master device to extend the number of addressable physical devices on a data bus without modifying the number of address bits used to identify the various slave devices on the bus. The data bus extender of the present invention can be used in existing data bus systems with minimal impact as it does not require a change at the slave devices. A data bus address extender in accordance with the present invention may comprise an address stripper and a range select decoder wherein at least one of the address bits at the slave side of the bus is enabled by the range select decoder. The present invention also provides a method for extending the number of addressable communication devices on a data bus. In its broadest terms, the method can be described by the following steps: receiving an address at a master device; subdividing the addressable slave devices into a plurality of ranges; identifying an appropriate range in response to a first portion of the address; identifying a particular device within the identified range responsive to a second portion of the address; selecting an uniquely identified addressable slave device by enabling the address lines; and performing the data transfer.

System and method for extending the number of addressable physical devices on a data bus

Methods and systems for processing data are disclosed. An exemplary system for parsing and modifying data stored in an array of storage elements includes a parsing system configured to access the data stored in selected storage elements of the array of storage elements and output the data in one of a plurality of register formats and a write system configured to write data to selected storage elements of the array of storage elements, wherein the data is received in one of the plurality of register formats. The plurality of register formats includes a first set of register formats corresponding to a packed representation of the data and a second set of register formats corresponding to an unpacked representation of the data.

System and method for processing data

A one-wire protocol is described, wherein a one-wire bus has either a wired-AND configuration or a wired-OR configuration. In this protocol, data is encoded using time modulation. In one embodiment, two devices communicate with each other through the one-wire bus. One device is configured to transmit data by driving the one-wire bus high, while the other device is configured to transmit data by driving the one-wire bus low. In a preferred embodiment, transmission of data by each of the two devices is interleaved in such a fashion so that there is a bit-for-bit exchange between one device and the other device. In another embodiment, more than two devices may communicate through the one-wire bus.

System and method for communicating over a one-wire bus

A system and method for performing peak-to-average power ratio reduction in a transmitter using pulse amplitude modulation (PAM) encoding. Broadly, a transmitter is configured to perform active digital filtering to detect encoded data symbols that if uncorrected would lead to relatively high analog signal peaks in the data transmission. A prediction is made of the peak values that would be applied at the digital to analog converter (DAC) if the original output of the Tomlinson precoder was sent into the shaping filter. If the absolute value of the predicted peak value exceeds a threshold, a correction of a full 2L step is applied for one sample of the Tomlinson precoded stream. The correction step is applied in such a way as to reduce the resulting peak output. Two methods of predicting the peak values are presented. The first method segments the shaping filter into causal and non causal portions so that no extra delay is introduced. The second method uses a two-stage approach where a first pass provides symbols without correction, then corrected symbols are injected in a duplicate modulation filter (this implies an extra delay equal to the filter delay). A variation of the two-stage approach takes advantage of the linear aspects of the Tomlinson preceding.

System and method for peak to average power ratio reduction

A system and method for characterizing a transmission line in a digital subscriber line (DSL) system. Broadly, the method uses DSL system components, which are configured to perform time domain reflectometry (TDR), in order to determine transmission line characteristics.

System and method for phone line characterization by time domain reflectometry

In general, a system and method for implementing DSL support for use by a computer having a PCI bus is disclosed. A DSL modem is allowed to simultaneously communicate data to and from the computer. In a simplified embodiment, a DSL enabling device provides both data flow control and general control functions of the DSL modem. The DSL enabling device comprises a PCI DMA arbitrator, which determines the status of a temporary memory module in response to either a transmit request from a transmit control unit or a receive request from a receive control unit, thereby arbitrating between the two control units in order to access the temporary memory module. A read/write register specifies priority between the transmit control unit and the receive control unit, as well as specifying computer memory addresses to write to and setting memory cell length. A transmit RAM temporarily stores data from the computer to the DSL modem until such time as the DSL modem instructs the transmit control unit that the DSL modem is ready to receive the data. A receive RAM temporarily stores data from the DSL modem for transmission to the computer memory until such time that the PCI DMA arbitrator instructs the receive control unit that the temporary memory module is ready to receive such data after which time a single channel DMA transfers the data from the temporary memory module to the computer.

Peripheral component interconnect (PCI) single channel master direct memory access (DMA) serving two separate channels

In general, a system and method for providing PCI power management support without requiring a clock is disclosed. A computer is allowed to reside in a sleep mode and receive a power management event signal from an attached peripheral device in response to an external action request from an external source, thereby waking the computer and initializing device drivers to allow the peripheral device to perform predefined functions. During initiation of the power management system, the system provides a peripheral device with a PME_Status bit. In response to an external event, the peripheral device receives an external action request from the source of the external event. The peripheral device then sets the PME_Status bit and transmits a power management event (PME) signal to a computer operating system. Upon receiving the PME signal, the computer turns back on. The computer operating system then searches all peripheral devices connected to the computer for the set PME_Status bit. Upon finding the source of the PME_Status bit, the computer initializes a device driver, which is related to the peripheral device, thereby allowing the peripheral device to function accordingly and accommodate the external action request.

System and method to set PME&mdash;status bit and wake up the system, and selectively load device driver by searching who set the bit without requiring clock

In general, the system and method provides a balanced clock distribution between two devices. A first output buffer, located in a source chip, provides buffering of a clock signal, after which, the delayed clock signal is transmitted to a destination chip, as well as to a balancing buffer located in the source chip. In addition, a second buffer, also located in the source chip, provides buffering of a data signal, after which, the data signal is transmitted to the destination chip. Both the clock and the data signals are then further buffered by first and second input buffers respectfully, which are located on the destination chip. After the delayed clock signal has been received by the balancing buffer, the balancing buffer provides a balancing delay to the delayed clock signal in accordance with the delay provided by the first input buffer, located in the destination chip, so as to provide a balanced clock distribution between the source chip and the destination chip. This balanced clock signal is then transmitted to portions of the source chip, for use by particular modules in the source chip which require a clock signal.

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Metuchen, NJ, United States of America

Marc R Delvaux