Compagnie Honeywell Bull

Compagnie Internationale Pour L'informatique Cii-honeywell Bull

Marc Michel Appell

Benjamin S Franklin

John J Bradley

Jean-Claude Marcel Cassonnet

Jacques Michel Bienvenu

Georges Lepicard

Jean-Louis Bogaert

Philippe-Hubert De Rivet

Claude Massuard

Philippe D De Sabatier

David M Slosberg

An apparatus for enabling communication of information between processes being carried out on a computing system. Each process is assigned a control block including a specialized memory element. A process being executed modifies the state of each memory element if it discovers any information of interest to processes awaiting execution. Before the next process is executed, the memory element in its control block is tested to find out if the previously-executed process left any information of interest.

Apparatus and method for communication of information between processes

A procedure call mechanism implemented by hardware instructions and a hardware recognizable mechanism known as a stack. A procedure call is utilized by users who have written their programs in a modular way to pass from one program module to another, it is used by user programs to avail themselves of operating system services, and it is used by the operating system itself to achieve a responsive modular structure. The stack is a mechanism permitting the above to be done. A stack is a segment of memory and comprises a number of contiguous portions, known as stack-frames, which are accessed in last in, first out LIFO fashion. Each procedure call creates a stack frame, with subsequent procedure calls creating new stack frames; each exit deletes stack frames thus 'popping up' a previous stack-frame. Thus a history of calls is correctly maintained in order to allow a return.

Call and stack mechanism for procedures executing in different rings

Computer data and procedure protection by preventing processes from intering with each other or sharing each other's address space in an unauthorized manner is accomplished in hardware/firmware by restricting addressability to a segmented memory and by a ring protection mechanism. To protect information in segments shared by several processes from misuse by one of these processes a ring protection hardware system is utilized. There are four ring classes numbered 0 through 3. Each ring represents a level of system privilege with level 0 (the innermost ring) having the most privilege and level 3 (the outermost ring) the least. Every procedure in the system has a minimum and a maximum execute ring number assigned to it which specifies who may legally call the procedure. Also maximum write and read ring numbers specify the maximum ring numbers for which a write and/or read operation is permitted. Processes use a segmented address during execution wherein segment tables isolate the address space of the various processes in the system. Hardware checks that the address used by a process is part of the address space assigned to the process, and if the address is outside the prescribed address space, an exception occurs. A process cannot refer to data within the address space of another process because the hardware uses the segment table of the referencing process.

Protection of data in an information multiprocessing system by

A system and method for computer process control in a multiprogramming/multiprocessing environment is disclosed. Each process in the system is associated with a process control block (PCB) hardware structure which is identified by its logical address (J,P). The PCB acts as a virtual processor with null speed when, in fact, no real processor is assigned to the process. As utilized in a multiprogramming environment a virtual process (PCB) is substituted for the real processor (i.e. central processing unit, CPU) whenever the only job of the processor is to listen for a signal to be sent by another processor and to restitute the real processor to the process when, or after, the signal has arrived. The circumstances where a process starts using a processor solely as an 'ear' are as follows: A. when the process state switches from a running state to a waiting state; or B. when the process state switches from a running state to a suspended state. In both instances the CPU is given away and replaced by the PCB.

System of controlling procedure execution using process control blocks

A multiprogrammable/multiprocessing digital computer system having a process control block for each process in the system, wherein each process control block includes information which specifies the state of a processor at any given time. Associated with each process control block is a decor extension table having information to indicate whether a specified function, such as the emulation of another processor, may be executed in the system. A native mode instruction indicating a specified function for either one instruction or for a plurality of instructions, is first checked to determine proper format, after which a determination is made by means of the decor extension table, as to whether or not the system is capable of executing the specified function indicated by the native mode instruction. If such native mode is not erroneous and if there is a positive indication of executability of the specified function by the system, then the particular specified function, such as the emulation mode of another processor, is activated.

Method and apparatus for executing an extended decor instruction

There is disclosed an input/output controller for an information processing system comprising a main memory, a central processing unit, a peripheral controller and a plurality of peripheral units coupled to the central processing unit. In particular, the input/output controller comprises a plurality of physical channels disposed between the peripheral controller and the central processing unit, a plurality of logical channels for transmitting information with the central processing unit, and each uniquely associated with one of the peripheral units. The main memory stores a first table including a physical channel entry containing informaton relative to the plurality of physical channels and a second table including a logical channel entry containing information relative to the plurality of peripheral units. Further, there is included means for storing a channel control program to be executed by the input/output control system for selectively transferring data between the main memory and the peripheral controller by first connecting the input/output control system to a logical channel entry and placing the identified logical channel table into the means for storing for a subsequent execution.

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Paris, France

Marc Michel Appell