Qualcomm Incorporated

Analog Devices,inc.

Intel Corporation

Other

Marc M Hoffman

Jose Fridman

Ajay Anant Ingle

Deepak Mathew

John H Edmondson

Ke Ning

Srijesh Sudarsanan

Michael J Allen

William C Anderson

Mao Zeng

Hebbalalu S Ramagopal

Russell L Rivin

Gerald Sweeney

Sundar Rajan Balasubramanian

Yurong Sun

Wei Zhang

Hongfeng Dong

Lucian Codrescu

Charles P Roth

Ravi P Singh

David J Hoyle

Ravi Kolagotla

Raka Singh

Jianming Zhu

Vladimir Botchev

Saurabh Lahoti

Tien Dingh

Gabby Yi

Michael John Lopez

James Lee

Mansi Jain

Mark Cox

Seyedmehdi Sadeghzadeh

Russel Rivin

A device includes a processor and a memory configured to store instructions. The processor is configured to receive a particular instruction from among the instructions and to execute the particular instruction to generate first output data corresponding to a sum of first input data and second input data. The processor is also configured to execute the particular instruction to perform a divide operation on the second input data and to generate second output data corresponding to a difference of the first input data and a result of the divide operation.

Instruction applicable to radix-3 butterfly computation

An electronic device receives a single instruction to apply a neural network operation to a set of M-bit elements stored in one or more input vector registers to initiate a sequence of computational operations related to a neural network. In response to the single instruction, the electronic device implements the neural network operation on the set of M-bit elements to generate a set of P-bit elements by obtaining the set of M-bit elements from the one or more input vector registers, quantizing each of the set of M-bit elements from M bits to P bits, and packing the set of P-bit elements into an output vector register. P is smaller than M. In some embodiments, the neural network operation is a quantization operation including at least a multiplication with a quantization factor and an addition with a zero point.

Instruction set architecture for neural network quantization and packing

A device includes a vector register file, a memory, and a processor. The vector register file includes a plurality of vector registers. The memory is configured to store a permutation instruction. The processor is configured to access a periodicity parameter of the permutation instruction. The periodicity parameter indicates a count of a plurality of data sources that contain source data for the permutation instruction. The processor is also configured to execute the permutation instruction to, for each particular element of multiple elements of a first permutation result register of the plurality of vector registers, select a data source of the plurality of data sources based at least in part on the count of the plurality of data sources and populate the particular element based on a value in a corresponding element of the selected data source.

Permutation instruction

An apparatus includes one or more registers configured to store a vector of input values. The apparatus also includes a coefficient determination unit configured to, responsive to execution by a processor of a single instruction, select a plurality of piecewise analysis coefficients. The plurality of piecewise analysis coefficients includes one or more sets of piecewise analysis coefficients, and each set of piecewise analysis coefficients corresponds to an input value of the vector of input values. The apparatus further includes arithmetic logic circuitry configured to, responsive to the execution of at least the single instruction, determine estimated output values of a function based on the plurality of piecewise analysis coefficients and the vector of input values.

System and method for piecewise linear approximation

An example method of updating an output data vector includes identifying a data value vector including element data values. The method also includes identifying an address value vector including a set of elements. The method further includes applying a conditional operator to each element of the set of elements in the address value vector. The method also includes for each element data value in the data value vector, determining whether to update an output data vector based on applying the conditional operator.

Arbitrary size table lookup and permutes with crossbar

An example method for placing one or more element data values into an output vector includes identifying a vertical permute control vector including a plurality of elements, each element of the plurality of elements including a register address. The method also includes for each element of the plurality of elements, reading a register address from the vertical permute control vector. The method further includes retrieving a plurality of element data values based on the register address. The method also includes identifying a horizontal permute control vector including a set of addresses corresponding to an output vector. The method further includes placing at least some of the retrieved element data values of the plurality of element data values into the output vector based on the set of addresses in the horizontal permute control vector.

Vector indirect element vertical addressing mode with horizontal permute

Techniques are provided for executing a vector alignment instruction. A scalar register file in a first processor is configured to share one or more register values with a second processor, the one or more register values accessed from the scalar register file according to an Rt address specified in a vector alignment instruction, wherein a start location is determined from one of the shared register values. An alignment circuit in the second processor is configured to align data identified between the start location within a beginning Vu register of a vector register file (VRF) and an end location of a last Vu register of the VRF according to the vector alignment instruction. A store circuit is configured to select the aligned data from the alignment circuit and store the aligned data in the vector register file according to an alignment store address specified by the vector alignment instruction.

Vector register addressing and functions based on a scalar register data value

Systems and methods of data extraction in a vector processor are disclosed. In a particular embodiment a method of data extraction in a vector processor includes copying at least one data element to a source register of a permutation network. The method includes reordering multiple data elements of the source register, populating a destination register of the permutation network with the reordered data elements, and copying the reordered data elements from the destination register to a memory.

Systems and methods of data extraction in a vector processor

A method includes selectively coupling a first address line of a plurality of address lines and a second address line of the plurality of address lines to a first element bank of a plurality of element banks of a vector register file according to a selection pattern. The method also includes accessing data stored within the first element bank that is selectively addressed by the first address line via a single read port.

Selective coupling of an address line to an element bank of a vector register file

An apparatus includes selection logic configured to select a first subset of a first set of samples stored at a first set of registers. The first subset includes a first sample stored at a first register of the first set of registers and further includes a second sample stored at a second register of the first set of registers. The apparatus further includes shift logic configured to shift a second set of samples stored at a second set of registers. The apparatus further includes a channel estimator configured to generate a first value associated with a channel estimate based on the first subset and further based on a second subset of the shifted second set of samples.

Device and method for computing a channel estimate

A method includes executing a first instruction at a processor to perform a first fast Fourier transform (FFT) operation on a set of inputs in a time domain to produce data in a frequency domain, where the set of inputs is in a first order and where the data in the frequency domain is in a second order. The method also includes performing an operation on the data in the frequency domain to produce data in the frequency domain, where the data in the frequency domain is in the second order. The method includes executing a second instruction at the processor to perform a second FFT operation on the data in the frequency domain to produce data in the time domain, where the data in the time domain is in the first order.

Dual fixed geometry fast fourier transform (FFT)

Methods and an apparatus are provided for interpolation of pixels in a pixel array having rows and columns of pixels. The apparatus includes a shift register array to shift pixel values of the pixel array, the shift register array including two or more shift registers; an interpolation filter array interconnected to the shift register array, the interpolation filter array including one or more interpolation filters; and a controller configured to provide pixel values in columns of the pixel array from the shift register array to respective interpolation filters in a first mode and configured to provide pixel values in rows of the pixel array from the shift register array to respective interpolation filters in a second mode. The controller may be configured to supply vertical sub-pixel values from the shift register array to the interpolation filters to generate diagonal sub-pixel values.

Half pixel interpolator for video motion estimation accelerator

A method and apparatus utilizing a prediction guided decimated search motion estimation algorithm are provided. The prediction guided decimated search motion estimation algorithm generates a motion vector used to encode a macroblock in a frame from a video sequence. The algorithm includes generating full-pixel seed vectors, performing a full-pixel search around the generated seed vectors, which is followed by a fractional pixel search. The full-pixel seed vectors generated are a predicted motion vector and a hierarchical motion vector. A fractional pixel search may be conducted around a final motion vector generated by the full-pixel search and may include a half-pixel search and a quarter-pixel search. The prediction guided decimated search motion estimation algorithm can be implemented in both software and hardware. The algorithm is characterized by improved efficiency, scalability, and decreased complexity.

Motion estimation using prediction guided decimated search

A computation core includes a computation block, an addressing block and an instruction sequencer, which are coupled to a memory through a memory interface. The computation block includes a register file and dual execution units. The execution units include features for enhanced performance in executing digital signal computations. The computation core is configured for executing digital signal processor instructions and microcontroller instructions, while achieving efficient digital signal processor computation and high code density. A finite impulse response filter algorithm achieves high performance on the dual execution units.

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Boxborough, MA, United States of America

Marc M Hoffman