Credence Systems Corporation

Other

Marc Loranger

Lawrence A Kraus

Ivan-Pierre Batinic

Alexander H Slocum, Jr

Eric D Hobbs

Keith J Breinlinger

Tommie Edward Berry

Steven Robert Payne

James Kaylor Larson

Patricia Renee Justice

Adrian S Wilson

Hiralal Ranga

Gordon Edward Chenoweth

Devices under test (DUTs) can be tested in a test system that includes an aligner and test cells. A DUT can be moved into and clamped in an aligned position on a carrier in the aligner. In the align position, electrically conductive terminals of the DUT can be in a predetermined position with respect to carrier alignment features of the carrier. The DUT/carrier combination can then be moved from the aligner into one of the test cells, where alignment features of the carrier are mechanically coupled with alignment features of a contactor in the test cell. The mechanical coupling automatically aligns terminals of the DUT with probes of the contactor. The probes thus contact and make electrical connections with the terminals of the DUT. The DUT is then tested. The aligner and each of the test cells can be separate and independent devices so that a DUT can be aligned in the aligner while other DUTs, having previously been aligned to a carrier in the aligner, are tested in a test cell.

Test systems and methods for testing electronic devices

A system for testing an integrated circuit device under test (DUT) communicating though synchronous digital signals and through a high speed serialization/de-serialization (serdes) bus includes a serdes interface circuit for communicating with the DUT via the serdes bus and an integrated circuit (IC) tester for communicating with the DUT and with the serdes interface circuit via digital signals. State changes in the digital signals are synchronized to a clock signal within the IC tester. The serdes interface circuit receives instructions from the IC tester via at least one of the digital signals and responds to the instructions by transmitting data to the DUT via the serdes bus using appropriate serdes protocol, by receiving and storing data transmitted by the DUT via the serdes bus, and by thereafter forwarding the stored data to the IC tester via at least one of the digital signals.

Test system for integrated circuits with serdes ports

A flexible built-in self-test (BIST) circuit is incorporated into an integrated circuit (IC) for testing one or random access memories or other memories embedded in an integrated circuit regardless of the number, size or test requirements of the memories. Input data from a controller that may be conveniently partitioned among components internal and external to the IC, supplies data to the BIST circuit indicating the size of the embedded memories to be tested and selecting from among several modes of BIST operation.

Partitionable embedded circuit test system for integrated circuit

A field programmable gate array (FPGA) and a decryption circuit are implemented within a common integrated circuit (IC) or within separate ICs enclosed within a common IC package. The decryption circuit decrypts an input FPGA program encrypted in accordance with a particular encryption key and then writes the decrypted FPGA program into the FPGA. Thus an FPGA program encrypted in accordance with a particular encryption key can be used to program only those FPGAs coupled with a decryption circuit capable of decoding the encrypted FPGA program in accordance with that particular encryption key. Since the decryption circuit and the FPGA are implemented in the same IC, or within the same IC package, the decrypted FPGA program the decryption circuit produces cannot be readily intercepted and copied.

Field programmable gate array with program encryption

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Livermore, CA, United States of America

Marc Loranger