Atmel Corporation

Atmel Nantes Sa

Marc Laurent

Frode Milch Pedersen

Thierry Gourbilleau

Patrice Menard

Mickael Le Dily

Stefan Markus Schabel

Ronan Barzic

Olivier Husson

Thierry Delalande

Laurentiu Birsan

Jean-Sebastien Berthy

A microcontroller system includes a higher power reference voltage circuit and a lower power reference voltage circuit configured to draw less power than the higher power reference voltage circuit when enabled. The system includes a power state logic controller configured to enable the lower power reference voltage circuit to provide a first regulated voltage during a power saving mode, and, on exiting the power saving mode, enable the higher power reference voltage circuit to provide a second regulated voltage.

Reference voltage circuits in microcontroller systems

A system for configuring or testing memory may cycle a memory array while substantially concurrently performing other functional testing. In particular implementations, the system may configure, or cycle, a flash memory using a serial interface and test other functional units using the same serial interface substantially concurrently with cycling the flash memory. In some implementations, cycling the flash memory includes erasing and writing to the flash memory in specific patterns in order to dissipate charge that may have accumulated during a fabrication process.

Configuring flash memory

Writing to a page of flash memory may include receiving write commands that are substantially independent of an internal architecture of the flash memory. In certain embodiments, two operand flash commands are received at a flash controller from a remote controller. In various implementations, the writing process may further include translating each two-operand write command into architecture-dependent flash commands; executing the architecture-dependent flash commands to fill a page buffer associated with the flash memory; and subsequently transferring contents of the page buffer to the page of flash memory.

Writing to flash memory

A process for automatically detecting and configuring with the throughput of a network, in which a device: (a) goes into a listen mode; (b) obtains a triplet of successive transitions in a transmitted signal, the triplet delimiting first and second signal levels, one dominant and the other recessive; (c) measures the duration of each of the first and second levels; (d) as a function of the measured durations, obtains a new throughput configuration by determining values for parameters that define a bit length L; (e) validates the new throughput configuration; (g) if at least one throughput adaptation condition is verified, goes into a normal mode, otherwise obtains a next transition of the signal, which delimits with the last previous transition a new level of the signal, then measures the duration of the new level and reiterates steps (d) to (g) taking account of the new signal level.

Process for automatically detecting the throughput of a network, particularly of the can bus type and for configuring with the detected throughput by transition analysis, and corresponding device

Growing community of inventors

Nantes, France

Marc Laurent