Synopsys, Inc.

Marc Jeroen Geuzebroek

Hubertus Gerardus Hendrikus Vermeulen

Andre Krijn Nieuwland

Johannes Boonstra

Pieter Van Der Wolf

Memory arbiter with latency guarantees for multiple ports. A method of controlling access to an electronic memory includes measuring a latency value indicative of a time difference between origination of an access request from a port of a plurality of ports and a response from the electronic memory. The method also includes calculating a difference between the latency value for the port and a target value associated with the port. The method further includes calculating a running sum of differences for the port covering each of a plurality of access requests. Further, the method includes determining a delta of a priority value for the port based on the running sum of differences. Moreover, the method includes prioritizing the access by the plurality of ports according to associated priority values.

Memory arbiter with latency guarantees for multiple ports

A data processing systemcomprising a monitoris provided and corresponding system-on-chip, method for monitoring and computer program product. The data processing system comprises multiple processing devicesand a monitor. The monitor is configured to monitor characteristics of the data streams, occurring among the plurality of data processing devices. The monitor comprises a means to determine whether a system characteristic substantially deviates from an expected system characteristic and to raise an anomaly signal if so. The system characteristic depends on the first characteristic and the second characteristic. In this way the monitor increases robustness by monitoring for problems related to deviations in the relation between multiple data streams.

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Budel, Netherlands

Marc Jeroen Geuzebroek