Microsemi Corporation

Marc H Vandenberg

Dumitru Sdrulla

Bruce Odekirk

Eric Karlsson

A Vertical Multiple Implanted Silicon Carbide Power MOSFET (VMIMOSFET) includes a first conductivity semiconductor substrate, a first conductivity semiconductor drift layer on the top of the substrate, a multitude of second conductivity layers implanted in the drift layer. The body layer is where the channel is formed. A first conductivity source layer is interspaced appropriately inside of the second conductivity layers. A gate oxide of a certain thickness and another oxide of a different thickness, a greater thickness than the gate oxide, placed in between the body layers but in such way that its shape does not distort the gate oxide in the channel. A charge compensated body layer of the second conductivity formed outside of the channel region and only at specific high electric field locations in the structure. The device and the manufacturing method deliver a power SiC MOSFET with increased frequency of operation and reduced switching losses.

Low loss SiC MOSFET

A Vertical Power MOSFET (VDMOS) device with special features that enable the Power MOSFET or IGBT device to withstand harsh radiation environments and the process of making such a device is described. All implanted and diffused layers are 'self aligned' to a 'Sacrificial Poly' layer, which later on is removed, preparing the wafers for a &#x201c;late gate&#x201d; oxide to be grown. A starting material with graded doping profile in the epitaxial layer on the substrate is shown to increase the SEB capability of the Power MOSFET.

Pseudo self aligned radhard MOSFET and process of manufacture

A SiC Power Semiconductor device of the Field Effect Type (MOSFET, IGBT or the like) with 'muted' channel conduction, negative temperature coefficient of channel mobility, in situ 'ballasted' source resistors and optimized thermal management of the cells for increased Safe Operating Area is described. Controlling the location of the Zero Temperature Crossover Point (ZTCP) in relationship to the drain current is achieved by the partition between the &#x201c;active&#x201d; and &#x201c;inactive&#x201d; channels and by adjusting the mobility of the carriers in the channel for the temperature range of interest. The &#x201c;Thermal management&#x201d; is realized by surrounding the &#x201c;active&#x201d; cells/fingers with &#x201c;inactive&#x201d; ones and the &#x201c;negative&#x201d; feedback of the drain/collector current due to local increase of the gate bias is achieved by implementing in-situ &#x201c;ballast&#x201d; resistors inside of each source contact.

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Bend, OR, United States of America

Marc H Vandenberg