Sgs-Thomson Microelectronics Limited

National Semiconductor Corporation

Stmicroelectronics Gmbh

Sgs-Thomson Microelectronics S.a.

Marc H Ryat

Alan J Baker

A current bias, current sense magneto-resistive preamplifier for a hard disk drive and related methods preferably includes an MR sensor responsive to a current bias for sensing a change in magnetic data flux and responsively providing a change in electrical resistance. A preamplifying circuit is preferably connected to the MR sensor for providing the current bias thereto and for amplifying a detected change in electrical resistance. The preamplifying circuit includes a sensor biasing circuit for providing the current bias to the MR sensor and an amplifying output circuit for providing an amplified output signal representative of the detected change in current bias to the MR sensor. The sensor biasing circuit preferably includes a current source, a first amplifying circuit connected to the MR sensor for sensing the change in electrical resistance therefrom, and a second amplifying circuit having a first input connected to the first amplifying circuit and a second input connected to the current source. The sensor biasing circuit also includes a transconductance amplifying circuit connected to first and second outputs of the second amplifying circuit and having an output connected to the first amplifying circuit for providing an output current proportional to the voltage difference at the first and second inputs thereof. The preamplifier further includes a capacitor connected to the preamplifying circuit for providing stability to at least a portion of the preamplifying circuit.

Current bias, current sense for magneto-resistive preamplifier,

A read/write head for a magnetic medium magnetic is modified by the addition to it of a parallel-connected resistor and by the measurement of the difference in voltage at the terminals of this unit, on the one hand when the read/write head and the resistor are perfectly connected and, on the other hand, when one of the connections is in an open circuit condition or even in short-circuit condition with respect to ground. Consequently, a measurement is taken, preferably, of the state of connection of the read/write head when it is in read mode and not when it is in write mode. It is shown that far greater reliability in the detection of this type of defect is obtained, in avoiding false alarms.

Magnetic read/write head that detects open and short-circuits

An adaptive cable equalizer is provided with a simple architecture, wherein a single control structure: controls the adaptation of the filter for compensating for cable length while simultaneously compensating for process and temperature variations; optimizes the SNR at any cable length by controlling biasing current sources; and uses a two-stage architecture which eliminates start-up problems and optimizes output levels to obtain optimal dc restoration while simultaneously allowing for independent optimization of the output levels of the recovered data in accordance with other requirements as desired. An analog adaptive equalizing filter is used for accurately synthesizing the inverse transfer function of cables of variable lengths. Data rates up to and beyond 400 Mbps are supported and the adaptive behavior automatically compensates for different cable lengths as well as process variations (with respect to the process(es) used for fabricating the equalizer in a monolithic form) and temperature variations.

Adaptive cable equalizer

An integrated transconductor circuit in which the input transistor(s) passes a current across a reference resistor. This conventional arrangement produces current error terms of Vbe/R and Ib. According to the present invention, these terms are compensated by providing a compensation resistor which is matched to the first resistor, and a compensation transistor which is matched to the input transistor, interconnected to feed the appropriate current components to the output. For even better compensation, an additional transistor is optionally added to remove the effect of base current of the compensation transistor. In differential embodiments, the compensation resistor may be bridged or split. Zero, one, or more stages of current mirroring can optionally be used to provide the desired output.

Linear transconductors

A transconductor circuit has first and second half cascode mirror circuits. Each half cascode mirror circuit has a cascode transistor, an active transistor, a base current compensating transistor, and a current source connected at one side to a supply voltage and at another side to the cascode transistor. The cascode and active transistors are connected in series between the current source and a first reference potential node. The base current compensating transistor is connected between the supply voltage and the base of the active transistor, and has its base connected between the current source and the cascode transistor. The bases of the cascode transistors of the first and second half cascode mirror circuits are connected to a second reference potential. First and second output mirror circuits are connected to mirror a current in a respective active transistor of the first and second half cascode mirror circuits. When a balanced input voltage is applied to respective voltage input nodes between the cascode and active transistors, corresponding balanced output currents are produced by the first and second output mirror circuits. In floating implementation, a biasing current source is connected between the first reference potential node and ground, and a biasing circuit connected to reference the second reference potential to a potential on the first reference potential node. Since the circuit may be made entirely of NPN transistors, it can run much faster than if PNP transistors were employed. Since the circuit is operated as a 'quasi open-loop' circuit, the speed of operation is also enhanced. The circuit can be operated in class AB operation, if desired, or, if desired, in a class B--like mode of operation. Additionally, the output current is independent of the .beta. of the transistors, and the circuit can sink current to the physical limits of the active transistor components, thus enabling a high dynamic range of operation.

HCM based transconductor circuits

A PTAT current source has first and second current mirror circuits, each comprising a cascode transistor, an output transistor in series with the cascode transistor, and a base current compensating transistor having a control element connected to the cascode transistor on a side away from the output transistor, and a current flow path element connected to a current control element of the output transistor, the cascode transistors of the first and second current mirror circuits having differently sized emitter areas. A resistor is connected between the cascode transistors of the first and second current mirror circuits across which a differential current is developed. An output circuit develops a current in the output transistor of the second current mirror circuit. In one embodiment, a third mirror circuit is provided, to cancel a portion of an emitter current flowing in the output transistor of the second current mirror circuit.

PTAT current source

A logarithmic amplifier has first and second mirror circuits, each having active transistors interconnected by a resistor. The current input is applied within one of the mirror circuits so that a logarithmic function thereof is generated for output by an output current mirror circuit. The mirror circuits are similarly constructed with an active transistor, a cascode transistor, and a base current compensating transistor. The cascode and active transistors are connected in series between an input node and a reference potential, or ground, with the base current compensating transistor connected between a supply voltage source and a base of the active transistor. The base of the base current compensating transistor is connected to the reference current input node. Through modification of the basic circuit by injection of an input current to the active transistor with respect to the reference potential, an exponential converter is presented.

Logarithmic and exponential converter circuits

A wideband current multiplying divider circuit that produces an output current of any ratio to the input current has a first bipolar transistor and a first reference current source connected in series between a supply voltage and ground. A second bipolar transistor and a second reference current source are also connected in series between the supply voltage and around. A summation current source is connected at one side to ground and at the other side to a divided current path. A first resistor is connected in series with the station current source between a base of the first bipolar transistor and ground, and through which an input current can be connected to flow. A second resistor is connected in series with the summation current source between a base of the second bipolar transistor and ground, and through which an output current can be connected to flow. The ratio of the input to output currents is determined by the ratio of the first and second resistors, wherein the output current can be a multiplied or divided value of the input current. The first and second bipolar transistors are NPN transistors, and the first and second reference current sources source substantially equal reference currents. The circuit may further include a cascode circuit connected to substantially remove any Early effect error between the first and second bipolar transistors.

Resistor ratioed current multiplier/divider

A current source for producing a current that is proportional to absolute temperature (i.e., 'PTAT') is disclosed. The current source is based upon a circuit having a pair of current mirrors, one based upon MOS transistors and the other based upon bipolar transistors, where each of two legs in the current source include the series connection of one of the MOS transistors with one of the bipolar transistors. Further included in the disclosed circuit is a series connection of three MOS startup transistors, useful in starting up the current source in a non-critical manner. A startup current source, sourcing a non-critical startup current, turns on one of the MOS startup transistors that is connected in current mirror fashion with the MOS transistor current mirror, turning on both current mirrors. As the output current increases, the current through the MOS startup transistors also increases, until equilibrium is achieved. Early effects in the bipolar transistor current mirror are eliminated by maintaining the gate-to-source voltage of the MOS transistors equal, without requiring cascode transistors, and thus maintaining low voltage operating capability.

A digital-to-analog converter has a bias block that provides first and second voltage outputs, and a bit cell having a switch for selectively connecting either a first or a second summing node to a current flow path depending upon the state of a binary input signal. An output bipolar transistor and a current source are connected in series between a supply voltage and a reference potential. A first MOS transistor is connected in the current flow path with its gate connected to the bipolar transistor. A base current compensating second MOS transistor is connected between the supply voltage and a base of the output bipolar transistor with its gate connected to the first voltage output of the amplifier. A resistor is connected between the base of the output bipolar transistor and the second voltage output of the amplifier. When a plurality of bit stages are provided, the resistor of each of the plurality of bit cells is sized according to a position of its associated cell in the bit order. The resistors may be sized as a power of 2 according to a position of its associated cell in the bit order, or, except for a most significant bit cell may be sized 2 times larger than the resistor of the most significant bit cell, with a plurality of equally sized resistors connecting adjacent bit cells in an R-2R network.

Current-summing digital-to-analog converter with binarily weighted

A cascode mirror circuit, referred to as a 'half-cascode mirror', or 'HCM' has first (cascode), second (active), and third (base control) transistors. The cascode and active transistors are connected in series at a first node, the series being connected between a second node and a reference potential. The cascode transistors has its base connected to a second reference voltage. The base control transistor is connected between the supply voltage and a base of the active transistors, with its base connected between the first reference current source and the cascode transistor. Depending upon the selection of input and output signal locations, the circuit can perform various functions, including the generation of an output circuit that varies linearly, logarithmically, or exponentially with an input current, and the generation of an output voltage that varies linearly with the input current.

Wideband linear and logarithmic signal conversion circuits

A power amplifier has a signal input stage to which an input signal is applied to produce an input stage output. An input signal amplifier is connected to receive the input signal to produce an amplified input signal from an active device at an output of the input signal amplifier. A push-pull signal output stage has first and second transistors. The first transistor has a current path connected between a supply voltage and an output node, and the second transistor has a current path connected between a reference voltage and the output node. The amplifier output provides variable drive current directly to a base of the first transistor, thereby enabling increased drive current to be realized. The power amplifier also includes a common mode biasing circuit connected to bias the first and second transistors for class AB operation, and the input stage output provides a signal base drive current to the first transistor separate from the common mode biasing circuit. This further increases the drive current that can be supplied to the base of the first transistor. By virtue of the direct connection of the current path of the first transistor between the supply voltage and the output node, and its base connection to the output of the input signal amplifier, the voltage on the base of the first transistor is enabled to swing to within 1V.sub.ce SAT from the supply voltage.

Power amplifier having high output voltage swing and high output drive

An operational amplifier input stage has at least two positive input transistors and one negative input transistor for providing more accurate and efficient limiting or rectification in limiter and rectifier circuits. The two positive input transistors are connected in parallel having a common drain connected to one side of a load and the negative input transistor's drain is connected to the other side of the load. The sources of all transistors are connected to a common node which is connected to a constant current source. This arrangement enables simplistic high accuracy limiting and rectifier circuits, having a reduced number of extrinsic components, thereby reducing unwanted speed limitations, to be realized. The operational amplifier input stage is also very useful in low supply circuit applications.

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Santa Clara, CA, United States of America

Marc H Ryat