Qualcomm Incorporated

Marc Gerald Dicicco

Xiangdong Zhang

Xinwei Wang

James Francis Imbornone

Zhenying Luo

Frederic Carrez

Yongrong Zuo

Exemplary embodiments are related to switch linearizer. A device may include at least one switch. The device may further include a linearizer coupled to the at least one switch and configured to cancel at least a portion of distortion generated by the at least one switch in an off-state.

Switch linearizer

A step attenuator with constant input capacitance and having good performance is disclosed. In an exemplary design, an apparatus includes a step attenuator having a constant input capacitance for different amounts of attenuation. The step attenuator receives an input signal, provides a variable amount of attenuation for the input signal, and provides an output signal. The step attenuator may include a plurality of attenuator sections coupled in series. Each attenuator section may include a plurality of capacitors and may have the constant input capacitance. At least one of the plurality of attenuator sections may be selected or unselected to obtain a selected amount of attenuation for the step attenuator. An attenuator section may provide a predetermined amount of attenuation or a variable amount of attenuation when selected. The apparatus may further include a power detector that receives and determines the power of the output signal from the step attenuator.

Step attenuator with constant input capacitance

A device includes a first circuit path coupled to a first node and a second node, the first circuit path having at least one first varactor circuit configured to receive a first tuning voltage, the first circuit path having a resistor with a selectable value, and a second circuit path coupled to the first node and the second node, the second circuit path having at least one second varactor circuit configured to receive a second tuning voltage, the second circuit path having a capacitor with a selectable value.

Quadrature current-combining linearizing circuit for generating arbitrary phase and amplitude

Power detectors with temperature compensation and having improved accuracy over temperature are disclosed. In an aspect of the disclosure, variations of a power detector gain over temperature is reduced by varying both the gate and drain voltages of MOS transistors within a power detector. In an exemplary design, an apparatus includes at least one MOS transistor, which receives an input signal, detects the power of the input signal based on a power detection gain, and provides an output signal indicative of the power of the input signal. The at least one MOS transistor is applied a variable gate bias voltage and a variable drain bias voltage in order to reduce variations of the power detection gain over temperature. At least one additional MOS transistor may receive a second variable gate bias voltage and provide the variable drain bias voltage for the at least one MOS transistor.

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Dunstable, MA, United States of America

Marc Gerald Dicicco