Northrop Grumman Systems Corporation

Marc Eisenzweig Sherwin

Brian Paul Wagner

Narsingh Bahadur Singh

Andre E Berghmans

David A Kahler

David J Knuteson

Robert Miles Young

John V Veliadis

Bettina A Nechay

Robert Samuel Howell

Pavel Borodulin

Nabil Abdel-Meguid El-Hinnawy

Michael Edward Aumer

John Xavier Przybysz

Aaron A Pesetski

John D Adam

Eric Jonathan Stewart

Rowland C Clarke

Aaron Ashley Hathaway

Matthew Russell King

Michael Manuel Fitelson

Thomas J Knight

Ranbir Singh

Ty Richard McNutt

Edward R Engbrecht

Gregory R Boyd

Sean R McLaughlin

Harold Clifton Hearne, Iii

John J Talvacchio

Jerry W Hedrick

Michael J Lee

Stephen Van Campen

Zachary A Stegen

John R Mason, Jr

Evan B Jones

Mark S Usefara

Travis Randall

Ty R Mcnutt

A solid state cooler device is provided that includes a substrate, a first and second conductive pad disposed on the substrate, a first and second superconductor pad each having a side with a plurality of conductive pad contact interfaces spaced apart from one another and being in contact with a surface of respective first and second conductive pads, and a first and second insulating layer disposed between respective first and second superconductor pads, and respective ends of a normal metal layer. A bias voltage is applied between one of a first conductive pad or first superconductor pad and one of the second conductive pad or the second superconductor pad to remove hot electrons from the normal metal layer, and the contact area of the plurality of first and second conductive pad contact interfaces inhibits the transfer of heat back to the first and second superconductor pads.

Solid state cooler device

An integrated circuit includes a substrate material that includes an epitaxial layer, wherein the substrate material and the epitaxial layer form a first semiconductor material with the epitaxial layer having a first conductivity type. At least one nanowire comprising a second semiconductor material having a second conductivity type doped differently than the first conductivity type of the first semiconductor material forms a junction crossing region with the first semiconductor material. The nanowire and the first semiconductor material form an avalanche photodiode (APD) in the junction crossing region to enable single photon detection. In an alternative configuration, the APD is formed as a p-i-n crossing region where n represents an n-type material, i represents an intrinsic layer, and p represents a p-type material.

Nano avalanche photodiode architecture for photon detection

One embodiment of the invention includes a reconfigurable circuit comprising a phase-change material switch. The phase-change material switch includes an actuation portion configured to receive a control signal having one of a first state and a second state and to emit a first heat profile in response to the first state of the control signal and a second heat profile in response to the second state of the control signal. The phase-change material switch also includes a switch portion comprising a phase-change material in proximity with the actuation portion. The switch portion can be selectable between a conducting state in response to the first heat profile to conduct an input signal from an input to an output of the phase-change material switch and a blocking state in response to the second heat profile to substantially block the input signal from the input to the output.

Phase-change material reconfigurable circuits

A phase change material (PCM) switch is disclosed that includes a resistive heater element, and a PCM element proximate the resistive heater element. A thermally conductive electrical insulating barrier layer positioned between the PCM heating element and the resistive heating element, and conductive lines extend from ends of the PCM element and control lines extend from ends of the resistive heater element.

Phase change material switch and method of making the same

In an embodiment, a integrated semiconductor device includes a first Vertical Junction Field Effect Transistor (VJFET) having a source, and a gate disposed on each side of the first VJFET source, and a second VJFET transistor having a source, and a gate disposed on each side of the second VJFET source. At least one gate of the first VJFET is separated from at least one gate of the second VJFET by a channel. The integrated semiconductor device also includes a Junction Barrier Schottky (JBS) diode positioned between the first and second VJFETs. The JBS diode comprises a metal contact that forms a rectifying contact to the channel and a non-rectifying contact to at least one gate of the first and second VJFETs, and the metal contact is an anode of the JBS diode. A first electrical connection ties the gates of the first VJFET, the gates of the second VJFET, and the anode of the JBS diode to a common gate electrode and a second electrical connection ties the source of the first VJFET and the source of the second VJFET to a common source electrode.

Power switching transistors

A method for growing a SiC-containing film on a Si substrate is disclosed. The SiC-containing film can be formed on a Si substrate by, for example, plasma sputtering, chemical vapor deposition, or atomic layer deposition. The thus-grown SiC-containing film provides an alternative to expensive SiC wafers for growing semiconductor crystals.

Method of producing large area SiC substrates

Methods of producing polycrystalline and single crystal dielectrics are disclosed, including dielectrics comprising CaCuTiOor LaGaSiO. Superior single crystals are manufactured with improved crystallinity by atomic lattice constant adjustments to the dielectric and to the substrate on which it is grown. Dielectric materials made according to the disclosed methods are useful for manufacture of energy storage devices, e.g. capacitors.

High dielectric capacitor materials and method of their production

Growing community of inventors

Catonsville, MD, United States of America

Marc Eisenzweig Sherwin