Broadband Communications Products, Inc.

Marc E Sawyer

Paul W Casper

Jeffrey S Grant

To derive a clock embedded in a digital data stream, a variable data rate synchronizer includes a data rate estimator that derives an estimate of the data rate of data contained in the digital data signal, and a frequency estimator that derives an estimate of the frequency of the output of a voltage controlled oscillator. A phase lock loop includes a phase detector to which the digital data signal and the output of the voltage controlled oscillator are coupled and has an output coupled to a sweepable loop filter. The output of the loop filter is coupled to the voltage controlled oscillator. During an initital frequency acquisition mode, the sweep controller sequentially varies an analog voltage applied to the voltage controlled oscillator, until the estimate of the data rate effectively corresponds to the estimate of the frequency of the output of the voltage controlled oscillator. This terminates the frequency acquisition mode and initiates a phase acquisition mode, during which the sweep controller causes a sawtooth sweep of the loop filter, until the output of the loop filter corresponds to the actual frequency of said embedded clock signal, thereby locking the loop to the embedded clock.

Clock extractor for high speed, variable data rate communication system

A data and clock recovery arrangement, for a high speed fiber optic digital communication system in which a serial digital bit stream is pre-scramble encoded by interleaving complementary pairs of overhead bits between successive groups of data bits, and then scrambled and transmitted to a receive site, comprises a data rate independent variable bit rate synchronizer, a descrambler and a decoder. The data rate independent variable bit synchronizer processes the received scrambled and encoded digital bit stream to derive a variable data rate synchronization clock signal. The synchronizer is capable of accepting any data rate within the operational data clock signal range of the system, and automatically tunes itself to the data clock signal embedded in the received scrambled and encoded serial data stream, so as to output respective scrambled and encoded serial data and clock signals. The descrambler descrambles the scrambled and encoded serial digital bit stream using the variable data rate synchronization clock signal, and the decoder decodes the descrambled serial digital bit stream to extract groups of data bits exclusive of the complementary pairs of overhead bits and to derive an output clock signal having a frequency coincident with the data rate of the data bits.

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Melbourne, FL, United States of America

Marc E Sawyer