Bull Hn Information Systems, Inc.

Marc E Sanfacon

Jeffrey S Somers

Raymond D Bowden, Iii

Edward R Salas

George J Barlow

Michelle A Pence

A method and apparatus for resetting memory state when power is applied to the system. The memory has memory elements, a refresh clock and a refresh counter for counting refresh cycles and providing refresh signals to the memory elements, the memory elements and refresh means being connected from the power system and from a battery back-up means. A state detection means is connected from the refresh counter for detecting a change in state of the refresh counter to a state equivalent to the reset state of the refresh counter and asserting a state change signal. A means responsive to the state change signal and to the occurrence of the reset signal provides a memory controller reset signal, so that the memory controller reset signal occurs in synchronization with the change of state of the refresh counter to a state equivalent to the refresh counter reset state. The memory reset further includes a time-out counter means responsive to the assertion of the reset signal and to the refresh clock for counting refresh cycles in synchronization with the refresh counter. A time-out detection means is responsive to the time out counter means for providing a time out signal when the time-out counter has counted a refresh period plus one clock cycle and to the state change signal for providing the memory controller reset signal when the time-out counter has counted a refresh cycle plus one clock period and the state change signal has not been asserted.

Method and apparatus for resetting a memory upon power recovery

In accordance with the present invention, there is provided a system for logging an error that occurred in a multi-chip memory storage device in a data processing system. The system has a mechanism for detecting an error and for receiving data and check bits associated therewith. The mechanism for detecting an error generates syndrome bits as a function of the data and of the check bits. Connected to the error detecting mechanism is an error logging mechanism which is adapted to receive the syndrome bits and to determine the chip in which the error occurred.

Memory controller with error logging

A system and method for detecting an error that occurred in a multi-chip memory storage device in a data processing system. The system detects an error and receives data and check bits associated therewith. A process that uses the principle of scrubbing and incorporates high speed error flags distinguishes between hard and soft errors.

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Acton, MA, United States of America

Marc E Sanfacon