Sun Microsystems, Inc.

Marc E Levitt

Sridhar Narayanan

Farideh Golshan

Sandeep K Aggarwal

Ramachandra P Kunda

Srinivas Nori

Adam C Malamy

Slobodan Simovich

David F Bertucci

Harsimran Singh Grewal

A method for controlling a gating circuit of an electronic system incorporating a scan architecture complying with IEEE Standard 1149.1 such that the gating circuit applies mutually exclusive signals to, for example, a decoded multiplexer. The gating circuit receives input signals from flip-flops that are part of a scan chain, is selectively controllable by a control signal to transmit predetermined mutually exclusive signals to the select inputs of the multiplexer during a scan mode. Alternatively, the gating circuit is controllable by the control signal to pass the input signals to the multiplexer in a normal operation or test mode. A mutual exclusivity circuit is provided to generate the control signal. During the scan mode, the control signal is generated at a first logic level such that the gating circuit transmits the predetermined mutually exclusive signals to the multiplexer while test values are being scanned into the flip-flops. Upon transition from the scan mode to the normal operation mode, the control signal is changed to a second logic level for a predetermined time period, and then changed back to the first logic level. When the control signal is at the second logic level, the gating circuit passes the input signals to the multiplexer, and the electronic system operates to propagate response signals that are applied to, for example, the scan chain flip-flops. In some instances, these response signals received by the flip-flops are not mutually exclusive, and the multiplexer may be damaged. The predetermined time period is set to apply the predetermined mutually exclusive signals before this possible damage occurs.

Method for ensuring mutual exclusivity of selected signals during

A circuit is disclosed which allows an IN-Test to be performed on an integrated circuit (IC) without having to stop the external clock sources by disabling the IC's internal phase-locked loops. Information indicative of the IC's clock mode and of the desired stop mode is contained within the IC's clock control register. In one embodiment, the internal clocks may be stopped in either of three stop modes while operating in one of three clock modes. When it is desired to stop the IC's internal clocks, the clock control register provides a stop instruction signal STOP.sub.-- INSTR to a clock control circuit which, depending upon the particular stop mode and clock mode encoded in signal STOP.sub.-- INSTR by the clock control register, asserts a enabling signal to a disable clock circuit. In response to this active-high enabling signal, the disable clock circuit asserts a zero feedback signal to the internal phase-locked loops of the IC and thereby forces the voltage controlled oscillators within the phase-locked loops to hold internal clocks low. In this manner, the IC internal clocks may be stopped to allow a test vector to be scanned out of the IC during an IN-Test without stopping the external clock source.

Clock stopping schemes for data buffer

A circuit for locally ensuring mutual exclusivity of selected signals during scan testing is coupled between an IEEE 1149.1 TAP controller and a conventional gating circuit. The mutual exclusivity circuit includes an AND-gate, an inverter, a first scan flip-flop and a second scan flip-flop. The first and second flip-flops have their scan-input leads hardwired to receive logic '1' and logic '0' signals, respectively. The first flip-flop also has its data input lead hardwired to receive a logic '0' signal. During the scan mode, the AND-gate receives a conventional rst.sub.-- tri.sub.-- en signal from the TAP controller. Thus, the AND-gate outputs a local.sub.-- rst.sub.-- tri.sub.-- en signal identical to the rst.sub.-- tri.sub.-- en signal. After the test pattern is scanned in, the rst.sub.-- tri.sub.-- en signal transitions to a logic '1' level, causing the local.sub.-- rst.sub.-- tri.sub.-- en signal to transition to a logic high level, which allows the test pattern to propagate through the circuit under test. At the leading edge of the capture pulse, the circuit enters the normal functional mode in which the second flip-flop stores and outputs the logic '1' signal outputted by the first flip-flop. After the propagation delay from the second flip-flop and the inverter, this logic '1' signal is inverted, causing the AND-gate to output the local.sub.-- rst.sub.-- tri.sub.-- en signal at a logic '0' level. This propagation delay is predetermined to allow the response data to be captured in the scan chain without damaging the circuit device requiring mutually exclusive signals, thereby removing the response data constraint on the test pattern.

Mutual exclusivity circuit for use in test pattern application scan

A circuit for coupling a LIC driver to a IEEE 1149.1 boundary scan implementation includes a logic circuit that converts the data and oe signals of the IEEE 1149.1 specification to test 'q.sub.-- up' and 'q.sub.-- dn' signals meeting the requirements of the LIC driver. These test 'q.sub.-- up' and 'q.sub.-- dn' signals are selectively provided to the LIC driver during boundary scan testing of the output driver. In a further refinement, the logic circuit also converts functional q.sub.-- up and q.sub.-- dn signals provided by the circuit under test to the data and oe signals of the IEEE 1149.1 specification. The logic circuit allows the widely used IEEE 1149.1 boundary scan standard to be used with LIC drivers. The resulting compatibility simplifies the testing and use of the LIC drivers, and provides a new boundary scan standard for use with LIC drivers that is compliant with the IEEE 1149.1 standard.

Boundary-scan circuit for use with linearized impedance control type

A method for coupling a linear impedance control (LIC) type output driver to IEEE 1149.1 boundary scan circuitry includes entering a boundary scan load mode to load a test pattern into a chain of boundary scan registers (BSRs). The test pattern includes values corresponding to output enable and data signals according to the IEEE 1149.1 standard. Then these data and output enable signals from the BSRs are converted into test 'q.sub.-- up' and 'q.sub.-- dn' signals meeting the requirements of the LIC driver. These test 'q.sub.-- up' and 'q.sub.-- dn' signals are selectively provided to the LIC driver during boundary scan testing of the LIC driver. In a further refinement, the method enters a boundary scan capture mode to capture the response (i.e., the functional q.sub.-- up and q.sub.-- dn signals) of the circuit under test to input test patterns shifted into the BSRs. The functional q.sub.-- up and q.sub.-- dn signals are converted into response data and oe signals complying with the IEEE 1149.1 specification, which are then captured in the BSRs. Thus, this method allows the widely used IEEE 1149.1 boundary scan standard to be used with LIC drivers. The resulting compatibility simplifies the testing and use of the LIC drivers, and provides a boundary scan standard for use with LIC drivers that is compliant with the IEEE 1149.1 standard.

Method for interfacing boundary-scan circuitry with linearized impedance

Circuits and methods of testing an integrated circuit die are disclosed. Active logic setting circuits are incorporated into input cells of a die. During testing, the active logic setting circuits weakly drive the input cells to a definite logic level. Therefore, the necessity of connecting probes to all of the input pads to prevent floating signals in the die is eliminated. Furthermore, during normal operations the active logic setting circuits have little or no effect on the performance of the die.

Method and apparatus for on die testing

A control circuit to stop an integrated circuit internal clock includes a signal distribution trace connected to a clock stop pipeline. The signal distribution trace creates a large phase delay signal for a first integrated circuit internal clock cycle which activates the clock stop pipeline, and a small phase delay signal for a final integrated circuit internal clock cycle that deactivates the clock stop pipeline. The clock stop pipeline includes a first circuit component to generate an intermediate stop instruction in response to a clock stop command and the large phase delay signal of the first integrated circuit internal clock cycle. The intermediate stop instruction proceeds through the clock stop pipeline in response to clock cycles following the first clock cycle. The clock stop pipeline includes a final circuit component to produce a final stop instruction when the intermediate stop instruction and the small phase delay signal of the final integrated circuit internal clock cycle are received at the final circuit component. The final stop instruction is used to lock the integrated circuit internal clock in a single digital state.

Control circuit for deterministic stopping of an integrated circuit

An integrated circuit includes a first metal layer with first layer identification signal writing circuitry connections to produce first metal layer circuit identification signals. The integrated circuit also has a second metal layer with second layer identification signal writing circuitry connections to produce second metal layer circuit identification signals. Logic circuitry in the first metal layer has input connections to the first layer identification signal writing circuitry connections and the second layer identification signal writing circuitry connections. The logic circuitry combines the first metal layer circuit identification signals and the second metal layer circuit identification signals to produce a circuit identification number. The value of the circuit identification number can be changed by altering the first layer identification signal writing circuitry connectors or the second layer identification signal writing circuitry connections. Thus, the value of the circuit identification number can be easily changed at the metal layer at which revisions are made.

Integrated circuit with identification signal writing circuitry

High speed scan testing is facilitated by pipelining or distributing a scan enable signal to scan circuits through a distribution network. The pipeline is formed from a plurality of scan enable distribution circuits residing on an integrated circuit to be scan tested. Preferably, before reaching the scan circuits, the scan enable signal passes through an equal number of the scan enable distribution circuits. The distribution network of the scan enable distribution circuits take a multitude of forms. The invention allows at-speed toggling of a scan enable signal as well as shifting of test data at functional system frequencies, while maintaining compatibility with test modes such as IEEE Standard 1149.1. The invention is also capable of supporting skewed-load and broad-side delay test modes.

Pipelined scan enable for fast scan testing

Lists of candidate faults within an integrated circuit are generated, for the purpose of fault diagnosis, by performing a partial intersection of fault lists output from a full-scan test such as a JTAG test. The fault lists represent all candidate faults which may be responsible for producing a mismatched bit between an output test vector and an expected test vector provided by the full-scan test. The partial intersection is performed by first determining the number of occurrences of each candidate fault within all lists associated with each mismatched bit. Then, only faults which occur at least a pre-selected number of times are selected. In this manner, lists of candidate faulty gates are generated based on the relative degree of intersection between fault sets. The lists of candidate faulty gates are input to an X-Y location tool which determines the physical location on the integrated circuit of each of the candidate faulty gates to facilitate the efficient examination of each of the candidate faulty gates by test personnel.

Method and apparatus for identifying faults within a system

A logic signal validity verifier for use in determining the validity of the logic states of a group of logic signals includes an inactive signal fault monitor for determining when all of the logic signals are in an inactive signal state and an active signal fault monitor for determining when more than one of the logic signals are in an active signal state. Where the logic signals are differential, the logic signal validity verifier further includes a differential signal fault monitor for determining when corresponding pairs of the differential logic signals are in the same active or inactive signal state.

Logic signal validity verification apparatus

A method and apparatus is disclosed for advantageously implementing a full boundary scan test of input and bi-directional paths of an integrated circuit. The present invention provides a full boundary scan test capability with practically no degradation of speed of operation during normal operation of the integrated circuit. Within the integrated circuit under test, boundary scan registers are coupled to each input and bi-directional pin. When placed in a test mode, the corresponding output drivers are tristated for every bi-directional pin of the integrated circuit under test. Then the values of a test signal vector asserted on the pins of the integrated circuit are captured by the boundary scan registers. These captured values are retrieved and output from the integrated circuit so that they can be compared to the asserted test signal vector. Because the integrated circuit does not have any non-test specific output pins, there is no need to override values output from the integrated circuit during a full boundary scan test. Furthermore, because the boundary scan registers capture the test signal vector values but cannot override values, the prior art need to provide a multiplexer in the path of each pin in order to make a full boundary scan test is eliminated. Therefore, the present invention permits a full boundary scan test without placing an overhead penalty on each path to and from the pins of the chip.

Method and apparatus for interconnect testing without speed degradation

Two related methods and apparatus for determining a binary constant to be output from embedded memory arrays into system logic of an integrated circuit when the system logic is being tested, that maximizes improvement to fault coverage of the system logic, are disclosed. The present invention has particular application to digital system testing. The fault coverage of the system logic is improved due to its controllability and observability are indirectly enhanced by the enhanced controllability of the embedded memory arrays. The first related method and apparatus determines the binary constant based on a testability measure selected for the system logic. The second related method and apparatus determines the binary constant based on results from automated test patterns generation for the integrated circuit. Both methods and apparatus provide a constant that is more effective than a randomly assigned binary constant, but without the expensive computations required for a binary constant determined from all possible enumeration.

Maximizing improvement to fault coverage of system logic of an

A method and apparatus for improving the testability of system logic of an integrated circuit having embedded memory arrays is disclosed. The embedded memory arrays are coupled to a binary constant generation and selection circuit which is also coupled to the system logic. During a test mode, the selection circuit sends a binary constant to the system logic in lieu of normal operational data output from the memory arrays. The system logic is tested while the binary constant is continuously applied.

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Sunnyvale, CA, United States of America

Marc E Levitt