Sun Microsystems, Inc.

Marc E Lamere

Julie M Staraitis

Micah C Knapp

Spencer Montgomery Gold

Matthew E Becker

Poonacha P Kongetira

Jason Eisenberg

Harry R Fair

Jonathan A White

A superscalar processor having a content addressable memory structure that transmits a first and second output signal is presented. The superscalar processor performs out of order processing on an instruction set. From the first output signal, the dependencies between currently fetched instructions of the instruction set and previous in-flight instructions can be determined and used to generate a dependency matrix for all in-flight instructions. From the second output signal, the physical register addresses of the data required to execute an instruction, once the dependencies have been removed, may be determined.

Superscalar processor having content addressable memory structures for determining dependencies

Methods and systems for improving a logic circuit are described. By using a voltage reducer for connecting a power-supply to a virtual ground, the voltage reducer reduces the voltage supplied by the power-supply to the virtual ground during one phase of the clock, thereby increasing the speed and efficiency of the logic circuit.

Virtual ground circuit

A memory array includes a plurality of memory cells logically arranged in M rows and N columns, wherein N is the number of memory cells per word of digital information and M is the number of words within the array. A plurality of N data output lines are associated with each of the N columns of the array for selectively retrieving output data from a word located at a predetermined word address in the array. Each data output line is selectively shared by each of the M memory cells within its associated column. Each of the cell output lines of the M memory cells in each of the N columns are logically OR-ed together to provide the output data retrieved by each data output line associated with each of the N columns.

System and method for accessing a memory array which tolerates non-exclusive read select enables

A memory device that combines RAM and ROM devices into a single memory array is provided. The memory array includes a memory cell for the RAM that is associated with a first bit line and a first word line. The memory array also includes a second memory cell for the ROM that is associated with a second bit line and a second word line. The first bit line and the second bit line are connected with each other. The second memory cell is provided with a circuit that discharges the second bit line to represent a logical value &ldquo;0&rdquo; in response to a signal from the second word line.

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Carlisle, MA, United States of America

Marc E Lamere