Western Digital Corporation

Aristos Logic Corporation

Marc E Acosta

Carl Bonke

Robert L Horn

Virgil V Wilkins

Patrick J Lee

Richard William Hull

Trinh C Bui

Joanne Wu

Stanley Chang

Vafa James Rakshani

Michael R Spaur

Jin H Hwang

Sanjay S Mathur

Phong Tran

Patrick D Conley

Ronald E Wilson

An integrated I/O controller in an integrated circuit is provided for centralized data management. The integrated circuit includes a host interface, a disk interface, and a mapping controller implemented in hardware to speed data processing and provide fault tolerance as exemplified with RAID configurations. The mapping controller provides block mapping across a plurality of peripherals or disk drives in a disk array. The integrated I/O controller can be utilized in storage area network systems and network area storage systems as well as other networking systems or devices.

Integrated input/output controller

A system for and method of increasing performance and manageability of storage area networks using optimized cache setting and handling policies. Initial cache management policies are set on a volume or zone basis, performance statistics are gathered based on preset statistical criteria, and policies are then set according to the goal of reaching particular system performance goals. Cache performance is optimized by customizing individual cache policies according to the underlying processing needs of each volume or sub-volume within the networked storage system. Cache parameter settings are optimized in a different way depending on whether the bulk of commands processed in the volume or sub-volume are pseudo-sequential or random, as well as other system-specific considerations.

Method of increasing performance and manageability of network storage systems using optimized cache setting and handling policies

A disk drive having an embedded servo disk format preferably having a fixed-number of radial servo sample wedges per track, in which data blocks are located independently of the servo sample wedge locations of any particular track, and can be split around servo sample wedges. Thus, a fraction of a data block, or more than one data block, can be written between consecutive servo sample wedges, beginning almost anywhere in a data wedge. Each data sector has an associated identification (ID) field that includes at least one segment descriptor. Each segment descriptor describes the data segments into which a data block can be split. Provision is made for as many segment descriptors as there can be data segments for a data block. In general, a segment descriptor is a multi-bit digital signal that defines the absolute or relative location of split data segments (or, alternatively, the absolute or relative length of split data segments, from which the location can be determined). A disk system in accordance with the present invention can be independently optimized for flux changes per inch and tracks per inch, and the size of each data sector can be varied. The invention permits 'defect swallowing', by allowing a data sector to be split around small defects within a data wedge of a track, and 'wedge push down' defect management, in which a data segment can be started at a next servo sample wedge if a large defect occurs in the previous data wedge.

Disk drive employing dynamically reconfigured read channel to process a

An intelligent disk drive employing a controller which performs high speed error correction and miscorrection detection using a finite field processor. The error correction code is defined over a finite field and the error detection code is defined over an extension field of the finite field. The finite field processor performs calculation over both the finite field and extension field to provide high speed error correction and correction validation.

Disk drive with fast error correction validation

An intelligent disk drive includes a controller which embeds user data address information into error correction code check symbols written to the data storage disk. The address information is not written to disk, but address errors are detected by decoding the error correction code check symbols during read operations. Disk space is saved while maintaining robust address error detection.

Disk drive with error code embedded sector identification

A format for embedded servo track identification fields in rotating disk data storage units such as magnetic disk drives. The present invention uses the concept of tri-bits (i.e., three code bits per logical bit) to encode track identification information in servo wedges of embedded servo disk drive systems. More specifically, two particular sets (and their equivalents) of tri-bit codes have been discovered to have optimum characteristics for providing a phase coherent encoding of a Gray code that is simple to translate into straight binary code. The properties of such tri-bit encoding limit error propagation to a single bit, which allows for very reliable track identification during movement of a head transducer across tracks (i.e., 'seeks'). A full range of Gray scale codes is available since more than two consecutive logical '0's can be reliably decoded when encoded using such tri-bits. The properties of such tri-bit encoding also allow for relatively high servo channel rates, which results in a reduction in servo field length. Accordingly, a counter-intuitive result of increasing the length of the encoding symbols for track identification fields is to decrease the overall length of the servo field, thereby permitting an increase in areal density.

Tri-bit encoding for disk drive servo track ID information

Access to a buffer memory is provided by a controller architecture and method employing an arbiter state machine for control of data transfer between multiple external peripheral devices and the dynamic random access memory buffer. Data transfer channels for each peripheral device include a first-in, first-out sub-buffer. Each data transfer channel communicates transfer requests to the arbiter when data is present in the FIFO. When data transfer to or from the FIFO nears an overrun or underrun condition, the data channel issues an urgent request to the arbiter state machine. The arbiter state machine prioritizes data transfer requests for enabling transfer between the buffer memory and data channels. Once a data transfer is in process it continues uninterrupted unless an urgent request is received from another device. In addition, the invention includes a refresh circuit for the dynamic RAM incorporating similar request and urgent request signals provided to the arbiter state machine for resolution.

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San Clemente, CA, United States of America

Marc E Acosta