Arista Networks, Inc.

Marc Durrenberger

Andrew Bruce Bridger

Liam Toby Warburton

Shih-Chien Chang

Systems and methods for communicating data via a multilane data link from a first clock domain to a second clock domain, where the data streams of a multilane link are clocked into FIFO deskew buffers using clock signals that are recovered from the data streams themselves. Each data stream is clocked into the deskew buffer with the clock signal recovered from that data stream. The data is clocked out of the deskew buffers using the clock signal of a target clock domain so that the data streams clocked out of the deskew buffers are synchronized with each other and with the clock signal of the target clock domain (the target clock signal) to eliminate the need for a separate clock domain crossing buffer.

Deskew and clock domain crossing for multilane link

Some embodiments provide a network device that may receive alignment information at each physical connection of a network interface of the network device. Each alignment information includes a unique value for identifying a unique logical lane associated with the corresponding physical connection. The network device may determine the order of the unique logical lanes associated with the several physical connections based on the received alignment information. The network device may configure a cross point switch of the network device to reorder the physical connections so that the unique logical lanes associated with the physical connections are ordered according to a defined order.

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Sydney, Australia

Marc Durrenberger