International Business Machines Corporation

Globalfoundries Inc.

Marc Douglas Knox

Dennis R Conti

David Lewis Gardell

David Michael Audette

Grant W Wagner

David A Grosch

Jody John Van Horn

Franco Motika

Paul Steven Zuchowski

Anne Elizabeth Gattiker

Phil Nigh

Normand Cote

Roger G Gamache, Jr

Paul M Gaschke

George J Lawson

Paul J Aube

Denis D Turcotte

Jeffrey P Gambino

John J Ellis-Monaghan

Kirk David Peterson

Jeffrey Donald Gelorme

Luc Gilbert Guerin

John B DeForge

Nathaniel R Chadwick

Erik A Nelson

Kathryn C Rivera

Mark R LaForce

Van Thanh Truong

Brian C Noble

Steve E Whitehead

Peter J Demko

Roger Gamache

Ezra D Hall

John A Fredeman

A wafer test device and methods of assembling a wafer test device involve a first laminate structure, and a second laminate structure arranged to interface with a microcircuit of the wafer. The wafer test device includes a compliant layer between the first laminate structure and the second laminate structure. The compliant layer includes an elastomer that exhibits compliance within a limited range of movement.

Compliant organic substrate assembly for rigid probes

Aspects of the invention include a method of tuning an interconnect that couples a first structure that is a first integrated circuit or a first laminate structure to a second structure that is a second integrated circuit or a second laminate structure. The method includes obtaining a compression requirement for a spring in a compliant layer of the interconnect. A longer path length of the spring leads to greater compression and mechanical support. Current and signal speed requirements for the interconnect are obtained. A shorter path length of the spring leads to greater current-carrying capacity and greater signal speed. Specifications for the spring are determined based on the compression requirement and the current and signal speed requirements. Determining the specifications includes determining a number of active coils of the spring to be less than two.

Interconnect and tuning thereof

A probe includes a pedestal and at least one feature extending from the pedestal to engage a surface of a corresponding contact at a position offset from a central longitudinal axis of the contact. The pedestal includes a cavity and the feature can include one or more blades that extend from a periphery of the cavity to a central longitudinal axis of the pedestal. The three blades are configured to engage the surface of the contact. The three blades can be positioned within the cavity to provide a 120-degree rotational symmetry about the central longitudinal axis of the pedestal.

Low force wafer test probe

A system for testing functionality of die on a wafer including a plurality of contacts includes a support structure and a plurality of probes mounted to the support structure in an array. A configuration of each of the plurality of probes varies based on a position of the probe within the array to maintain uniform engagement between the plurality of probes and a corresponding plurality of contacts across the array.

Low force wafer test probe with variable geometry

A probe includes a pedestal and at least one feature extending from the pedestal to engage a surface of a corresponding contact at a position offset from a central longitudinal axis of the contact.

A test circuit including a light activated test connection in a semiconductor device is provided. The light activated test connection is electrically conductive during a test of the semiconductor device and is electrically non-conductive after the test.

Light activated test connections

An assembly including a liquid thermal interface material for surface tension adhesion and thermal control used during electrical/thermal test of a 3D wafer and methods of use. The method includes temporarily attaching a thinned wafer to a carrier wafer by applying a non-adhesive material therebetween and pressing the thinned wafer and the blank silicon-based carrier wafer together.

Temporary liquid thermal interface material for surface tension adhesion and thermal control

Method and apparatus for margin testing integrated circuits. The method includes selecting a clock frequency, an operating temperature range and a power supply voltage level for margin testing an integrated circuit wherein one or more of the clock frequency, the operating temperature range and the power supply voltage level is outside of the normal operating conditions of the integrated circuit; applying an asynchronously time varying power supply voltage set to the selected power supply voltage level to the integrated circuit; running the integrated circuit chip at the selected clock frequency and maintaining the integrated circuit within the selected temperature range; applying a continuous test pattern to the integrated circuit; and monitoring the integrated circuit for fails.

Methods and apparatus for margin testing integrated circuits using asynchronously timed varied supply voltage and test patterns

Methods for testing a semiconductor circuit () including testing the circuit and modifying a well bias () of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control () of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.

Integrated circuit testing methods using well bias modification

A heat sink for use in the burn-in of an I/C chip, which chip has a generally 'flat' surface. The heat sink has a 'flat' surface with micro-channels therein, positioned to open and close in and out of contact against the flat surface of an I/C chip being burned-in. At least one liquid opening communicates with said essentially flat surface on the heat sink to continuously apply liquid between the heat sink and the chip. A liquid inlet is provided to supply liquid to said at least one liquid opening. A recovery channel is positioned to recover liquid from between the heat sink and the chip, and an exhaust member is provided to carry liquid from said recovery channel to the exterior of the heat sink. The invention also includes a method of burning-in a chip.

Liquid recovery, collection method and apparatus in a non-recirculating test and burn-in application

A method for testing a semiconductor circuit () including testing the circuit and modifying a well bias () of the circuit during testing. The method improves the resolution of IDDQ testing and diagnosis by modifying well bias during testing. The method applies to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control () of the well potentials during test. In general, the method relies on using the well bias to change transistor threshold voltages.

Integrated circuit testing method using well bias modification

A method, system and apparatus for testing an integrated circuit chip. The system including: means for forming a liquid polyalphaolefine layer on a bottom surface of the integrated circuit chip, a top surface of the integrated circuit chip having and a bottom surface not having signal and power pads; means for placing a surface of a heat sink into physical contact with the bottom surface of the polyalphaolefine layer; means for electrically coupling the integrated circuit chip to a tester; means for electrically testing the integrated circuit chip; means for electrically de-coupling the integrated circuit chip from the tester; means for removing the heat sink from contact with the polyalphaolefine layer, all or a portion of the polyalphaolefine layer remaining on the bottom surface of the integrated circuit chip; and means for removing the polyalphaolefine layer from the bottom surface of the integrated circuit chip.

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Hinesburg, VT, United States of America

Marc Douglas Knox