Intel Corporation

Infineon Technologies Ag

Intel IP Corporation

Marc Dittes

Georg Seidemann

Christian Geissler

Sven Albers

Andreas Wolter

Thomas Wagner

Klaus Reingruber

Richard Patten

Bernd Waidhas

Klaus Jürgen Reingruber

Carlo Marbella

Christian Georg Geissler

Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.

Package stacking using chip to wafer bonding

Disclosed is a package comprising a substrate having a patterned surface with an optical contact area, an optical redistribution layer (oRDL) feature, and a build-up material extending over the patterned surface of the substrate and around portions of the oRDL features. In some embodiments, the package comprises a liner sheathing the oRDL features. In some embodiments, the oRDL feature extends through openings in an outer surface of the build-up material and forms posts extending outward from the outer surface. In some embodiments, the package comprises an electrical redistribution layer (eRDL) feature, at least some portion of which overlap at least some portion of the oRDL feature. In some embodiments, the package comprises an optical fiber coupled to the oRDL features.

Integrated circuit packages including an optical redistribution layer

Semiconductor packages having variable redistribution layer thicknesses are described. In an example, a semiconductor package includes a redistribution layer on a dielectric layer, and the redistribution layer includes first conductive traces having a first thickness and second conductive traces having a second thickness. The first thickness may be different than the second thickness, e.g., the first thickness may be less than the second thickness.

Semiconductor package having a variable redistribution layer thickness

An electrical device includes a redistribution layer structure, an inter-diffusing material contact structure and a vertical electrically conductive structure located between the redistribution layer structure and the inter-diffusing material contact structure. The vertical electrically conductive structure includes a diffusion barrier structure located adjacently to the inter-diffusing material contact structure. Further, the diffusion barrier structure and the redistribution layer structure comprise different lateral dimensions.

Electrical device and a method for forming an electrical device

A method includes aligning a wire with a package body having a contact pad and moving the wire through the package body to form electrical contact with the contact pad.

Vertical wire connections for integrated circuit package

A microelectronic package is described with an illuminated backside exterior. In one example, the package has a package substrate, a die attached to the package substrate, a cover over the die and the package substrate, a lamp, and a screen over the die, externally visible and optically coupled to the lamp so that when the lamp is illuminated the illumination is externally visible through the screen.

Microelectronic package with illuminated backside exterior

A system-in-package device includes at least three electrical device components arranged in a common package. A first electrical device component includes a first vertical dimension, a second electrical device component includes a second vertical dimension and a third electrical device component comprises a third vertical dimension. The first electrical device component and the second electrical device component are arranged side by side in the common package. Further, the third electrical device component is arranged on top of the first electrical device component in the common package. At least a part of the third electrical device component is arranged vertically between a front side level of the second electrical device component and a back side level of the second electrical device component.

System-in-package devices and methods for forming system-in-package devices

A substrate and method of fabrication is disclosed. In one example, the substrate includes a first dielectric layer, a first and a second conductive trace arranged over the first dielectric layer and a second dielectric layer arranged between the first and second conductive traces and partially covering the first and second conductive traces, wherein an exposed part of the first and second conductive traces is exposed from the second dielectric layer at an interface and wherein a shape of the interface between the first and second conductive traces includes one or more of an angle, an edge, a curvature, a bulge, a step and an indentation.

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Wuppertal, Germany

Marc Dittes