Intel Corporation

Marc D Torrant

Paul Baleme

Joydeep Ray

Blaise B Fanning

Altug Koker

Jason W Brandt

David M Puffer

Inder M Sodhi

Russell Jerome Fenger

Michael Mishaeli

Aditya Sreenivas

Michael T Klinglesmith

Jorge E Parra

Ashish V Choubal

Zeev Offen

Bryan R White

Nagi Aboulenein

Daniel Greenspan

Todd M Witter

Ramadass Nagarajan

Deepak Samuel Kirubakaran

James A Coleman

Yoav Lossin

Ashraf H Wadaa

Noor Mubeen

Peter J Elardo

Neil Schaper

Eric A Geisler

Andrey Gabdulin

Lingjing Zeng

Ryan Thompson

Georgina Saborio Dobles

A processor core energy-efficiency core ranking scheme akin to a favored core in a multi-core processor system. The favored core is the energy-efficient core that allows an SoC to use the core with the lowest Vfor energy-efficiency. Such Vvalues may be fused in appropriate registers or stored in NVM during HVM. An OS scheduler achieves optimal energy performance using the core ranking information to schedule certain applications on the core with lowest V. A bootstrap flow identifies a bootstrap processor core (BSP) as the most energy efficiency core of the SoC and assigns that core the lowest APIC ID value according to the lowest V. Upon reading the fuses or NVM, the microcode/BIOS calculates and ranks the cores. As such, microcode/BIOS calculates and ranks core APIC IDs based on efficiency around LFM frequencies. Based on the calculated and ranked cores, the microcode or BIOS transfers BSP ownership to the most efficiency core.

Energy-efficient core voltage selection apparatus and method

An architecture and method for managing at least two distinct machines (or objects) in which resources are shared as a single entity (or object) in an agent-based system. The agent-based system comprising a controller, a local agent coupled to the controller, and at least one clustered machine. The at least one clustered machine includes at least two individual agents, the at least two individual agents sharing at least one shared resource/service. The system also includes a virtual non-persistent connection for coupling the at least two individual agents to the local agent. The at least one shared resource/service is accessed by the local agent through the virtual non-persistent connection using a virtual IP address to enable the at least two individual agents of the at least one clustered machine to be represented as a single object.

System and method for managing distributed objects as a single representation

A processing device comprises an instruction execution unit, a memory agent and pinning logic to pin memory pages in a multi-level memory system upon request by the memory agent. The pinning logic includes an agent interface module to receive, from the memory agent, a pin request indicating a first memory page in the multi-level memory system, the multi-level memory system comprising a near memory and a far memory. The pinning logic further includes a memory interface module to retrieve the first memory page from the far memory and write the first memory page to the near memory. In addition, the pinning logic also includes a descriptor table management module to mark the first memory page as pinned in the near memory, wherein marking the first memory page as pinned comprises setting a pinning bit corresponding to the first memory page in a cache descriptor table and to prevent the first memory page from being evicted from the near memory when the first memory page is marked as pinned.

Isochronous agent data pinning in a multi-level memory system

In an embodiment, a processor includes at least one core, a cache memory, and a cache controller. Responsive to a request to store an address of a data entry into the cache memory, the cache controller is to determine whether an initial cache set of the cache memory and corresponding to the address has available capacity to store the address. Responsive to unavailability of capacity in the initial cache set, the cache controller is to generate a first alternate address associated with the data entry and to determine whether a first cache set corresponding to the first alternate address has available capacity to store the alternate address and if so to store the first alternate address in the first cache set. Other embodiments are described and claimed.

Apparatus and method to dynamically expand associativity of a cache memory

Remapping technologies for execution context swap between heterogeneous functional hardware units are described. A computing system includes multiple registers configured to store remote contexts of functional units. A mapping table maps the remote context to the functional units. An execution unit is configured to execute a remapping tool that intercepts an operation to access a remote context of a first functional unit of the plurality of functional units that is taken offline. The remapping tool determines that the first functional unit is remapped to a second functional unit using the mapping table. The operation is performed to access the remote context that is remapped to the second functional unit. The first functional unit and the second functional unit may be heterogeneous functional units.

Execution context swap between heterogeneous functional hardware units

Multi-level memory architecture technologies are described. One processor includes a requesting unit, a first memory interface to couple to a far memory (FM), a second memory interface to couple to a near memory (NM) and a multi-level memory controller (MLMC) coupled to the requesting unit, the first memory interface and the second memory interface. The MLMC is to write data into a memory page of NM in response to a request from the requesting unit to retrieve the memory page from FM. The MLMC receives a hint from the requesting unit and clears a writeback bit for the memory page indicated in the hint. The hint indicates that the data contained in the memory page of the NM is not to be subsequently requested by the requesting unit. The MLMC starts a writeback operation of a memory sector including the memory page and one or more additional memory pages. The writeback operation is to transfer the data contained in the memory page from the NM to the FM when the writeback bit is set and the writeback operation does is not to transfer the data contained in the memory page from NM to the FM when the writeback bit is cleared.

Writeback mechanisms for improving far memory utilization in multi-level memory architectures

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Sacramento, CA, United States of America

Marc D Torrant