Cypress Semiconductor Corporation

Silicon Light Machines Corporation

Juniper Networks, Inc.

Zilog, Inc.

Marc D Hartranft

Syed Tariq Shafaat

Brenor L Brophy

Jeff Hall

Andrew J Walker

Gautam Ganguly

Peng Su

Pat Zicolello

Keith A Garrett

Clinton Carlisle

Eric N Mann

Michael J Dueweke

Gerald Donal Murphy

Kevin J Gallagher

Dan Zupcau

Leo F Luquette, Jr

Helen L Turner

Scott Ward

Guhan Subbarayan

Gina Liao

Michael J Duewake

The disclosed apparatus may include (1) at least one alignment pin that (A) is placed proximate to a component on a circuit board and (B) is secured proximate to the component on the circuit board and (2) at least one heatsink that (A) is placed atop the component after completion of a reflow process in which the component is soldered to the circuit board, (B) is aligned by the alignment pin such that the heatsink resides in a specific position atop the component, and (C) absorbs heat dissipated by the component when the component is operational. Various other apparatuses, systems, and methods are also disclosed.

Apparatus, system, and method for precise heatsink alignment on circuit boards

The disclosed apparatus may include (1) a stiffening brace that (A) is coupled to a top surface of a lidless integrated circuit and (B) includes at least one joint and (2) a removable lid that (A) interfaces with the stiffening brace at the joint, (B) temporarily sits atop the stiffening brace during a reflow process in which a bottom surface of the lidless integrated circuit is soldered to a circuit board, and (C) provides structural support to the lidless integrated circuit to impede the lidless integrated circuit from warping during the reflow process. Various other apparatuses, systems, and methods are also disclosed.

Apparatus, system, and method for mitigating warpage of lidless integrated circuits during reflow processes

A method and apparatus to provide electrostatic discharge (ESD) protection to electronic circuits using a combination of low voltage and high voltage transistors.

Cascode combination of low and high voltage transistors for electrostatic discharge circuit

An architecture and method are provided for preventing snapdown in a voltage controlled MEMS device having a movable actuator with an actuator electrode coupled to a high voltage power supply (HVPS) through a drive circuit, the movable actuator suspended over a cavity electrode formed on a substrate and coupled to a common backplane supply (VssC). Generally, the circuit includes a number of first diodes coupled between the HVPS and the actuator electrode and/or the cavity electrode to provide a forward-biased path to transfer a positive charge to the HVPS when the accumulated charge exceeds a predetermined threshold. Preferably, the drive circuit further includes second diodes to provide a low impedance path to transfer a positives charge from the actuator electrode and/or the cavity electrode to a substrate ground when the accumulated charge results in or exceeds a predetermined threshold voltage. Other embodiments are also disclosed.

Snapdown prevention in voltage controlled MEMS devices

A circuit and method are provided for preventing snapdown in a voltage controlled Micro-Electromechanical System device having a movable actuator with an actuator electrode coupled to a first potential, the actuator suspended over a cavity electrode coupled to a second potential. Generally, the circuit includes an in-circuit conductive path between the actuator electrode and the cavity electrode, the conductive path configured to transfer charge therebetween when a voltage between the first and second potential exceeds a predetermined threshold voltage. In one embodiment the conductive path comprises an ESD clamp coupled between the actuator electrode and the cavity electrode. Other embodiments are also disclosed.

Circuit and method for snapdown prevention in voltage controlled MEMS devices

A circuit () can include a first section () that can provide a designated function within an integrated circuit device that can be altered due to current injection at a node (). A mirror section () can mirror the effects of current injection on one or more devices within first section () and generate an output indication INJ_EFF representing such effects. In one very particular arrangement, detection of an injected current can be used to prevent false triggering of a switched electrostatic discharge (ESD) current path.

ESD trigger circuit with injected current compensation

The quality and reliability of electro-optical modules can be improved, for instance, through improved testing and burn-in of an electro-optical sub-assembly. Reliability can also be enhanced through better methods of constructing an electro-optical module. By arranging both an electrical interface and an optical interface on a sub-assembly, for instance, testing can be performed on both interfaces in a single testing process. Burning-in an electro-optical sub-assembly can also improve the reliability of the module by identifying defects. A method of forming an electro-optical module can provide improved reliability by testing and/or burning-in an electro-optical sub-assembly before assembling the module.

Methods of improving reliability of an electro-optical module

An arrangement for optical communication comprises an optical coupler, an opto-electronic board, and an optical fiber. The optical fiber comprises a first refraction surface, a second refraction surface, and an internal reflector. The first refraction surface has a first finite focal length. The second refraction surface has a second finite focal length. In operation, an optical signal enters the first refraction surface, couples from the first refraction surface to the second refraction surface via the internal reflector, and exits the second refraction surface, where the optical signal defines a light path. The light path optically couples the opto-electronic board to the optical fiber.

Optical communication arrangement

A method of manufacturing a plurality of electro-optical sub-assemblies in parallel is provided. A plurality of printed circuit boards (PCBs) are preferably formed in a panel of flex material. Rigid substrates can be arranged along regions of the PCBs. A plurality of electrical components, including electro-optical semiconductor devices, are preferably located on the rigid substrates. Lens arrays are preferably aligned over the electro-optical semiconductor devices, such as through an alignment mechanism. The PCBs can then be singulated into individual electro-optical sub-assemblies. The rigid substrates can be a plurality of leadframes formed on a matrix leadframe. The matrix leadframe is preferably attached to the panel of flex material such that the leadframes are arranged in proximity to leadframe cutout regions of the PCBs. Electrical interconnections are then preferably formed between the electrical components on the leadframe and the PCBs.

Method of manufacturing electro-optical devices

An electro-optical apparatus constructed according to various inventive principles disclosed herein provides flexibility in the type and arrangement of components. The electro-optical apparatus preferably includes a Printed Circuit Board (PCB). An interface device can be electrically connected to the PCB, and an electro-optical device can be electrically connected to the interface device. A lens is preferably arranged in optical communication with the electro-optical device. Numerous variations in component selection and arrangement are contemplated within the scope of these inventive principles. Various methods for configuring an electro-optical apparatus are also provided.

Electro-optical apparatus

An electro-optical device preferably includes a printed circuit board (PCB) having a cutout region or a rigid region. A leadframe having an electro-optical semiconductor device arranged thereon can be arranged in proximity to the cutout region of the PCB. Alternatively, the electro-optical device can be arranged on the rigid region of the PCB. A lens is preferably arranged over the electro-optical semiconductor device. A connector array can also be arranged on the PCB to communicate electrical signals with an external device. An interface circuit, such as a driver circuit or an amplifier circuit, can also be arranged in close proximity to the electro-optical semiconductor devices on the leadframe or the PCB.

An anchor structure placed in an open field in corner areas of the semiconductor die and along die edges for preventing cracks in the die. In the corner areas, the anchor structure is placed perpendicular to a resultant vector force, which is approximately at a 45.degree. angle to an imaginary horizontal line passing through the die. This perpendicular placement of the anchor structure more uniformly distributes the stresses along the anchor preventing corner cracks in the die. Along the die edges, the anchor structures are placed approximately perpendicular to the resultant vector forces that impinge the die edges.

Method and apparatus for preventing cracks in semiconductor die

Protection of the thin gate oxide of MOS field effect transistors from irreversible puncture due to undesired high voltages and currents, generated by electrostatic discharge through handling or otherwise, is provided by a two stage circuit that operates to shunt thousands or tens of volts around the protected transistors. A first stage, employing a thick field effect transistor, protects against the very high voltage. A second stage, employing a thin field effect transistor, protects against lower but still excessive voltage. The protection circuit is formed as part of an integrated circuit chip by surrounding the lead bonding pad to which the protected transistors are connected.

Growing community of inventors

Scotts Valley, CA, United States of America

Marc D Hartranft