Dell Products Inc.

Dell USA L P

Marc D Alexander

Ricardo Luis Martinez

Todd Martin

Cynthia M Merkin

Lowell B Dennis

Matthew Bruce Mendelow

Todd W Schlottman

Orbie A Welch

MyPhuong N Sang

Colin McCann

Jonathan T Stern

Jay Baxter

Amy Christine Nelson

Kenneth W Stufflebeam, Jr

Lois D Mermelstein

Brian J Decker

Peter A Woytovech

Jonathan Adonis Kwahk

Douglas A Azzarito

Systems and methods for reducing problems and disadvantages associated with traditional approaches to encryption and decryption of data are provided. An information handling system may include a processor, a memory communicatively coupled to the processor, an encryption accelerator communicatively coupled to the processor, and a computer-readable medium communicatively coupled to the processor. The encryption accelerator may be configured to encrypt or decrypt data in response to a command from the processor to perform an encryption or decryption task upon data associated with an input/output operation. The computer-readable medium may have instructions stored thereon, the instructions configured to, when executed by the processor: (i) monitor for input/output operations occurring prior to loading of an operating system into the memory; and (ii) in response to detection of an input/output operation, communicate a command to the encryption accelerator to perform an encryption or decryption task upon data associated with an input/output operation.

System and method for pre-operating system encryption and decryption of data

An information handling system ('IHS') includes a processor and a memory device for storing instructions processable by the processor for causing the IHS to determine whether configuration of a basic input output system ('BIOS') has been modified. The instructions are also processable by the processor for causing the IHS to, in response to determining that the configuration has been modified, determine whether a previously stored configuration is likely a valid configuration. Moreover, the instructions are processable by the processor for causing the IHS to, in response to determining that the previously stored configuration is likely a valid configuration, store the configuration that has been modified in a new location of a storage device. Furthermore, the instructions are processable by the processor for causing the IHS to, in response to determining that the previously stored configuration is likely not a valid configuration, store the configuration that has been modified in a location of the storage device that stores the previously stored configuration.

Information handling system for storing basic input output system configurations

Bus numbering management for an information handling system, such as a personal computer, is provided by interfacing one or more selectively hidden devices with one or more buses through either a hardware or software implementation. If an inactive bus becomes active, then disabling of a selectively hidden device interfaced with another active bus provides a bus number to the newly active bus. For instance, if a graphics capability is added to a computer system through a PCI bus, a PCI bridge associated with a second PCI bus is disabled so that the PCI bus number for the portion of the second PCI bus between the chipset of the computer system and the PCI bridge is available for use as the PCI bus number for the PCI bus associated with the graphics capability. The PCI bus number for the portion of the second PCI bus between the PCI bridge and existing peripheral devices is available for use for both portions of the second PCI bus. Thus, peripheral devices associated with the second PCI bus will continue to be recognized by the operating system as associated with the same PCI bus number. Alternatively, instructions associated with the PCI bus controller enables or disables a virtual device by handling input/output accesses.

System and method for managing bus numbering

The present invention discloses an information handling system that reduces POST time in a boot operation. The information handling system includes a processor, a memory and a BIOS unit. The BIOS also includes memory test pointer and a test block size indicator. During the POST routine, the BIOS tests at least one test block during at least one idle period.

System and method for testing memory during boot operation idle periods

An information handling system comprises a first bus system comprising a plurality of connection pins wherein at least one pin is unused, at least one control line for controlling or communication with devices of the system, a controllable coupling/de-coupling unit for coupling/de-coupling the control line with the at least one previously unused pin, and a control unit for controlling the coupling/de-coupling unit coupled with the control line.

Information handling system with improved bus system

A power consumption manager and a power manager sequencer coordinate transition of information handling system components between active and inactive states to manage information handling system power consumption. The power manager transitions components to an inactive state upon a determination of inactivity and then shuts down, for instance by operating as a module in the BIOS. Activation of an I/O device, such as the power switch, restores the power manager to an active state to allow recovery of the information handling system to an operational status. The power manager sequencer detects activation of the I/O device to restore selected components to an active state substantially simultaneous with the power manager so that the selected components have power to accept recovery instructions from the power manager. For instance, a network interface controller receives power to recover from an inactive state before the BIOS sends a PCI bus reset command.

Method and system for information handling system component power management sequencing

A system and method for reducing the amount of time for a boot operation is provided that includes a test management module that divides the memory into multiple test blocks and then selects a limited number of test blocks to test during a boot operation, thereby decreasing the overall amount of memory test time.

System and method for testing memory

A system that includes a computer system configured to boot using a system firmware is provided. The system firmware includes instructions for causing the computer system to detect a test apparatus coupled to the computer system and initiate a manufacturing mode of the system firmware in response to detecting the test apparatus coupled to the computer system.

Automatically initiating a manufacturing mode of a system firmware

An information handling system is provided which includes a dynamic interrupt router for balancing interrupt assignments among a plurality of devices requesting interrupt assignments. The system balances interrupt assignments among both fixed devices mounted on the processor board and interrupt assignments to devices situated in expansion slots. When the system is populated with a large number of devices relative to the number of available interrupts, improved interrupt sharing is desirably achieved by causing a device which generates a large number of interrupt requests to share a common interrupt with a device which generates a lower number of interrupts.

Information handling system with dynamic interrupt allocation apparatus and methodology

A method is provided that includes booting a computer system using a first system firmware stored on a circuit coupled to the computer system and, in response to detecting a test apparatus coupled to the computer system, causing the first system firmware to be stored onto a device in the computer system.

System and method for providing information to a computer system

A method, computer program product, and system are provided that include reading a first indicator from a memory location, checking a first port associated with the first indicator for the presence of a peripheral device, and, in response to the peripheral device not being present on the first port, storing a second indicator associated with a second port in the memory location.

Method, computer program product, and system for detecting a peripheral device in a computer system

A system that includes a computer system configured to boot using a system firmware is provided. The system firmware includes instructions for causing the computer system to provide a control code to a test apparatus configured to perform a functional test on the computer system and receive information provided by the test apparatus in response to the control code.

System and method for receiving information from a test apparatus

A method and apparatus for implementing a BIOS-level floppy boot-sector virus prevention system. A floppy boot protection system installed on a computer system queries a user to indicate whether or not the computer system is to be booted from a floppy disk inserted in a floppy disk drive of the computer system prior to booting from the floppy disk. If the user responds in the affirmative, the computer system is booted from the floppy disk and operation proceeds as usual. If the user responds in the negative, the floppy disk boot is skipped, the user is advised of this fact, and the computer system attempts to boot from the next device listed in its boot table. In one aspect, during setup of the computer system, the user is able to enable or disable the floppy boot protection system as desired. If the user fails to respond to the query within a predetermined amount of time, the boot protection system defaults to skipping the floppy disk boot and proceeding as described above.

BIOS-level floppy boot-sector virus prevention

A computer system for executing BIOS code on a secure operating system, the computer system including a processor, memory coupled to the processor, at least one nonvolatile storage device, such as a hard disk drive, a BIOS file stored on the nonvolatile storage device, and a computer program executable by the processor wherein the computer program is capable of locating BIOS code within the BIOS file and copying the BIOS code to an executable program file stored on the nonvolatile storage device which is executed by the processor. Also, a method of executing BIOS code on a secure operating system that locates the BIOS code within at least one BIOS file, copies the BIOS code to an executable file, and executes the resulting executable file on a processor.

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Cedar Park, TX, United States of America

Marc D Alexander