Texas Instruments Corporation

Marc Couvrat

Frederic Boutaud

Jason A Jones

Mansoor A Chishtie

Gilbert Laurenti

Jean-Pierre Giacalone

Shigeshi Abiko

Gael Clave

Yves Masse

Emmanuel Ego

Oliver Mougenot

Gerard Chauvel

Douglas E Deao

Mark L Buser

Eric L Badi

Ajay J Padgaonkar

Herve Catan

Laurent Le-Faucheur

Armelle Laine

Karim Djafarian

Vincent Gillet

Anne Lombardot

Francois Theodorou

Alain Boyadjian

Jean-Marc Philippe Bachot

Alain Vallauri

Jean-Louis Tardieux

Laurent Ichard

Eric Ponsot

Jack Rosenzweig

Walter A Jackson

Shintaro Mizushima

Frederic Nidegger

David Russell

N M Ganesh

An execution unit for a processing engine comprising first head part circuitry for deriving an intermediate signal from an input signal. The execution unit also comprises further circuitry which receives the intermediate signal and operates on it to produce a final signal. The further circuitry is typically configured to perform one or more signal processing functions in combination with the first circuitry, and generally comprises separate circuitry for each function. The intermediate signal is configured to be usable by each of the separate circuitry.

Bit field processor

Apparatus and methods are presented to allow the creation of a personalized audio signal for a communication device., An option to record audio input and create a call signal audio file is selected via an input mechanism ( ). Audio input is recorded when a record button ( ) is pressed and the recording is terminated when the record button ( ) is pressed a second time. Processing circuitry ( ) optionally applies audio compression, filtering and encoding algorithms to said audio input and creates a call signal audio file. The call signal audio file is then stored in the memory circuitry designated for call signal audio files ( ). Additional audio output circuitry ( ) plays the call signal audio file when an incoming call is detected by the transceiver ( ).

Personalized incoming call signal for communication devices

A processor ( ) is provided that is a programmable fixed point digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. The processor includes an instruction buffer unit ( ), a program flow control unit ( ), an address/data flow unit ( ), a data computation unit ( ), and multiple interconnecting busses. Dual multiply-accumulate blocks improve processing performance. A memory interface unit ( ) provides parallel access to data and instruction memories. The instruction buffer is operable to buffer single and compound instructions pending execution thereof. A decode mechanism is configured to decode instructions from the instruction buffer. The use of compound instructions enables effective use of the bandwidth available within the processor. A soft dual memory instruction can be compiled from separate first and second programmed memory instructions. Instructions can be conditionally executed or repeatedly executed. Bit field processing and various addressing modes, such as circular buffer addressing, further support execution of DSP algorithms. The processor includes a multistage execution pipeline with pipeline protection features. Various functional modules can be separately powered down to conserve power. The processor includes emulation and code debugging facilities with support for cache analysis.

Microprocessors

A circuit for interfacing a processor with a host processor is provided that has a memory associated with the processor that is selectively accessible by either both the processors or by the host processor, a plurality of storage devices selectively interconnectable with the memory and host processor, and a logic circuit interconnected with the storage devices and processors for interconnecting at least a portion of the storage devices to the memory in response to signals from the processors. An integrated circuit is provided that has a microprocessor, a memory associated with said processor that is selectively accessible by said microprocessor or a host processor, a plurality of storage devices selectively interconnectable with said memory and said host processor, and a logic circuit interconnected with said storage devices and interconnectable with said processors for interconnecting at least a portion of said storage devices to said memory in response to signals from said processors.

Host port interface

An arithmetic circuit is provided in which the circuit scale can be reduced and the circuit delay can be shortened. The upper 24 bits and lower 16 bits of the 40 bit data A and B, that is input into the arithmetic circuit 100, are calculated in the first arithmetic circuit 110 and the second arithmetic circuit 120, respectively. The carry transmission control circuit 130 transmits the carry between the arithmetic circuit 120 and the arithmetic circuit 110 when the arithmetic circuit dividing signal p does not divide the arithmetic circuit, and the command control circuit 140 outputs an identical command to each of the arithmetic circuits. As a result, this circuit becomes an arithmetic circuit of 40 bits. The carry transmission control circuit 130 stops the transmission of the carry between the arithmetic circuit 120 and the arithmetic circuit 110 when the signal p divides the arithmetic circuit, and the command control circuit 140 outputs each of the independent commands to each of the arithmetic circuits. As a result, this circuit becomes a parallel arithmetic circuit of 24 bits and 16 bits.

Arithmetic circuit

An electronic device for transferring data between a serial port and a memory of a CPU is provided having a plurality of data registers for transferring data between said serial port and said memory in response to a first set of control signals, a data bus connected to said registers and said memory for passing data to and from said memory in response to a portion of said first set of control signals, first control circuitry for generating said first set of control signals and for generating at least one interrupt to said CPU, at least one control register connected to said first control circuitry for providing mode control information to said first control circuitry, a plurality of address registers for storing data address, at least one address generator connected to said address registers for automatically generating addresses in response to a second set of control signals, an address bus connected to said address registers, and second control circuitry connected to said address generator, a portion of said control register and said first control circuitry for generating said second set of control signals.

System having registers for receiving data, registers for transmitting

Modulator especially for digital cellular telephone systems, characterised in that it comprises a programmable peripheral processor (25) carrying out, with the same circuits, the modulation function and the channel coder/decoder tasks.

Modulator especially for digital cellular telephone system

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Saint Laurent du Var, France

Marc Couvrat