Commissariat a L'energie Atomique

Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Stmicroelectronics S.a.

Apibio

Marc Belleville

Cyril Condemine

Olivier Thomas

Nicolas Pierre Delorme

Dominique Morche

Philippe Pantigny

Arnaud Laflaquiere

Fabien Clermidy

Hervé Fanet

Joel Hartmann

Philippe Flatresse

Pascal Besesty

Laurent Alacoque

Sigrid Thomas

Alexandre Valentian

Rodolphe Heliot

Sylvain Majcherczak

Dimitri Soussan

Elisabeth Orsier

Bettina Rebaud

Philippe Maurine

Vincent Liot

Santhosh Onkaraiah

Claudine Jaffard

Catherine Bour

Pierre Castelein

Jo&euml;l Hartmann

Philippe Lionel Maurine

An electronic circuit including a bipolar switching memory device including first and second electrodes at terminals of which a programming voltage can be applied, the circuit including: a first mechanism applying, to the first electrode, a data signal having, during a time period d, a constant state 0 or 1; a second mechanism applying, to the second electrode, a control signal that alternates, during time period d, between state 1 and state 0, the control signal being same regardless of the state in which the memory device is programmed; a selection device allowing a current to flow into the memory device during a programming time included in time period d; and a change of state of the control signal taking place during the programming time.

Method for programming a bipolar resistive switching memory device

Adiabatic logic circuit having a first and a second inputs, a first and a second outputs and at least one supply and synchronization input (Phi), with this circuit comprising:

Low consumption logic circuit with mechanical switches

Neuromorphic circuits are multi-cell networks configured to imitate the behavior of biological neural networks. A neuromorphic circuit is provided which comprises a network of neurons each identified by a neuron address in the network, each neuron being able to receive and process at least one input signal and then later emit on an output of the neuron a signal representing an event which occurs inside the neuron, and a programmable memory composed of elementary memories each associated with a respective neuron. The elementary memory, which is a memory of post-synaptic addresses and weights, comprises an activation input linked by a conductor to the output of the associated neuron to directly receive an event signal emitted by this neuron without passing through an address encoder or decoder. The post-synaptic addresses extracted from an elementary memory activated by a neuron are applied, with associated synaptic weights, as inputs to the neural network.

Electronic circuit with neuromorphic architecture

An integrated circuit may include a digital output port including a buffer stage that includes subassemblies of MOSFET transistors. One subassembly may include two pull-up transistors having sources connected to a common high voltage, and having drains connected to a common node connected to the output terminal. Another subassembly may include pull-down transistors having sources connected to a common low voltage, and having drains connected to the common node. The pull-up and pull-down transistors are formed in a thin semiconductor layer of an FDSOI substrate. The substrate may include a thick semiconductor layer and an oxide layer separating the thin and thick semiconductor layers. Areas of the thick semiconductor layer facing the pull-up and pull-down transistors may be connected to a circuit configured to vary a threshold voltage of the pull-up and pull-down transistors.

Integrated circuit comprising at least one digital output port having an adjustable impedance, and corresponding adjustment method

The invention relates to the asynchronous communication of data in complex integrated systems, be it inside integrated circuit chips or between integrated circuit chips, for example in a compact stack of chips. According to the invention, the transmission is done on a single conductor of exchanges. The data are transmitted on this conductor in the form of at least three levels of potential, the first level representing a first value of data item transmitted, the second representing a second value of data item transmitted, and the third representing an inactive level. An acknowledgment signal is transmitted on the same exchange conductor as the data. This signal is preferably sent by the receiver in the form of the forcing of the exchange conductor by the receiver to the inactive potential level, the sender detecting this forcing.

Method and device for asynchronous communication of data on a single conductor

A digital electronic circuit includes: a plurality of sequential elements; at least one data-conducting path connecting an input sequential element to a destination sequential element; a clock outputting a clock signal on a clock tree for setting the speed of the sequential elements; a monitoring device receiving, as an input, at least one data signal traveling on a conducting path and arriving at a destination sequential element, the monitoring device including: a module for defining at least one detection window according to the clock tree; and a detector for detecting a transition of each data signal received during a detection window; and wherein each detection window is defined so as to enable the detection or anticipation of a fault corresponding to a violation of the rise time or the maintenance time of a data signal relative to a clock signal edge received by the destination sequential element receiving the data signal.

Device for monitoring the operation of a digital circuit

A method for testing a variable capacitance measurement system including a fixed voltage source, a variable capacitance sensor, and a circuit to process information output by this sensor. The method connects an electrically controllable electronic simulation device to replace the variable capacitance sensor, models the electrophysical behaviour of the sensor, and tests the system.

Test method for a variable capacitance measuring system

A circuit for biasing the bulk of a MOS transistor, including a capacitive element connecting the bulk of the MOS transistor to a source of an voltage.

Method and device for adapting the voltage of a MOS transistor bulk

This invention relates to an improved microelectronic RAM memory device, provided with 4T or 6T cells made using the double gate technology and each associated with two word lines.

Memory cells in double-gate CMOS technology provided with transistors with two independent gates

An accelerometric measurement device with a return loop including accelerometer, a corrector generating a signal for correction of the position of the accelerometer, a closed return loop to apply this correction signal to the accelerometer, a detector to detect an error in operation of the accelerometer, and a modifying component making at least a first modification to operation of the corrector from its initial state to a modified operating state.

Accelerometer in closed loop with error detection

Method for controlling an analogue switch including a transistor to which a variable analogue input voltage Vin is applied on a first terminal between a source terminal and a drain terminal of the transistor while a second terminal between the drain and the source terminal is at a variable output voltage V, including the steps of: during a first phase, applying a first voltage to the transistor gate, the first voltage equal to a sum of or a difference between Vin and a first constant potential V, and configured to make the transistor conduct; and during a second phase, applying a second voltage to the transistor gate, the second voltage equal to a sum of or a difference between V, Vin and a second constant potential V, and configured to block the transistor, the difference between the first voltage and the second voltage being constant.

Control method for an analogue switch

A sigma-delta modulator comprising: According to the invention, at least one resonator in the modulator is chosen from among the group comprising mechanical, acoustic, electromechanical, electrostatic, optical and chemical resonators. Application to analogue-digital conversion, signal detection and signal generation.

Bandpass sigma-delta modulator and uses of the sigma delta modulator for conversion, detection and production of signals

A process for selective deposition of material on electrodes of chips made from a single substrate. The process includes forming a plurality of chips on the same substrate. Each chip includes a plurality of electrodes, address pads, and an address area containing the programmed address of the chip. The address areas are connected to the address pads and capable of recognizing the address of the chip to activate the chip. The process also includes establishing electrical connections to connect the address pads and the plurality of electrodes on each chip for the activation of the chips and polarization of the electrodes. Further, the process includes addressing the chips and electrodes on which a first material is to be deposited, and simultaneously depositing the first material on the addressed electrodes of the activated chips. The addressing and deposition steps are repeated as many times as necessary to make material depositions on the other electrodes.

Process for selective deposition of material on biosensor or chip electrodes made on the same substrate

Device converts an analogue signal representing charges resulting from the photo-detection of electromagnetic radiation into a digital signal. Device includes (a) a number of photo-detectors connected in rows and columns through of buses, the photo-detectors in one column sharing the same column bus, itself connected to an output stage by through a row bus, and between each photo-detector and the column bus, (b) an integrator, to integrate the charges arriving from the photo-detector, (c) means for resetting the integrator, and (d) a comparator to compare the voltage Vfrom the integrator with an internally predefined threshold voltage V, characterized in that it also includes a processing device, a clock, the clock controlling the processing device and the processing device receiving a binary value present at the output of the comparator at each signal from the clock.

Method for converting an analog signal into a digital signal and electromagnetic radiation sensor using same

The invention relates to an electrically erasable, non-volatile memory device, having a memory cell of the floating gate type ( ), defined by a source zone, a drain zone, a channel zone ( ) and a control gate zone ( ), the latter being separated from the channel zone by an insulation zone ( ), said five zones being implemented in a semiconductor film formed on an insulating layer ( ), said memory cell being laterally insulated by one or more insulation zones ( ) in contact with the insulating layer.

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Saint Egreve, France

Marc Belleville