Huawei Technologies Co., Limited

University of Toronto

Huawei Technologies Canada Co., Ltd.

Marc-Andre Lacroix

Davide Tonietto

Semyon Lebedev

Henry Wong

Euhan Chong

Anthony Chan Carusone

Petar Ivanov Krotnev

MohammadMahdi Mohsenpour

Luke Wang

Babak Zamanlooy

Systems and circuits for an asynchronous SAR ADC are described. The SAR ADC includes a two-stage comparator with a preamplifier first stage and a latch second stage. The preamplifier first stage is activated by an active pulse of a first clock signal and the latch second stage is activated by an active pulse of a second clock signal. The Done signal from a done detector is fed back as the active pulse of the first clock signal. The leading edge of the active pulse of the second clock signal is driven by the leading edge of the active pulse of the first clock signal via an RS latch. The Done signal is further fed back through the RS latch to drive a trailing edge of the active pulse of the second clock signal.

Asynchronous SAR ADC using two-stage comparator having separate resets

There is provided an integrated loopback used for on-die self-test and diagnosis of transceiver faults. According to embodiments, there is provided an interface network including an AC coupling capacitor interposed between input pins of the interface network and an input of an amplifier, a shunt capacitor interposed between the AC coupling capacitor and the input of the amplifier and a selector. The selector includes a mission mode circuit component connected to a bottom plate of the shunt capacitor and the selector is configured to select between a first mode and a second mode, wherein the first mode is mission mode and the second mode is loopback mode, wherein in the second mode the mission mode circuit component forms at least part of a circuit that supplies a loopback signal.

On-die input capacitive divider for wireline receivers with integrated loopback

The disclosed systems, structures, and methods are directed to a two wire-based clock multiplication unit (CMU), employing a first phase lock loop (PLL) configured to generate a first high-speed clock frequency fencoded in differential mode, a second PLL configured to generate a second high-speed clock frequency fencoded in common mode, and a summer configured to combine the differential mode encoding the first high-speed clock frequency fand the common mode encoding the second high-speed clock frequency fand transmit the combined differential and common mode high-speed clock frequencies on a two wire-based conductor bus. In addition, systems, structures, and methods directed to a two wire-based clock recovery module and a two wire-based clock recovery module have also been disclosed.

Method and apparatus for simultaneous propagation of multiple clockfrequencies in serializer/deserializer (SerDes) Macros

A method includes deactivating transmitters of a first plurality of transceivers that are associated with an endpoint to multi-channel communication fabric. A given transceiver of the first plurality of transceivers includes a receiver. The method includes controlling the given transceiver to cause the given transceiver to couple a reference source of the given transceiver to a first node of the receiver, measure a first value at a second node of the receiver, and determine a gain between the first node and the second node based on the measured first value. The method includes controlling the given receiver to cause the given receiver to isolate the reference source from the first node of the receiver; and measuring, by the given transceiver, a second value at the second node and determining, by the given transceiver, an intrinsic noise based on the measured second value. The method includes activating the deactivated transmitters; measuring, by the given transceiver, a third value at the second node and determining, by the given transceiver, a composite noise based on the measured third value; and determining, by the given transceiver, a crosstalk noise at the first node of the receiver based on the determined gain, the determined intrinsic noise and the determined composite noise.

Methods and systems for in-situ crosstalk measurements in communication systems

The present disclosure relates to an analog-to-digital converter (ADC) and a method for controlling an ADC. The ADC includes a plurality of quantization levels for analog-to-digital conversion. The ADC is adapted for utilizing a subset of the plurality of quantization levels for analog-to-digital signal conversion. The subset is formed by selecting at least one level to be deactivated using a greedy search method and deactivating the at least one level. The method includes using a subset of the plurality of quantization levels for analog-to-digital signal conversion, the subset being formed by selecting at least one level to be deactivated using a greedy search method and deactivating the at least one level.

Analog-to-digital converter and control method thereof

Methods, systems and devices for dynamically controlling resolution of an analog-to-digital converter (ADC). The ADC receives an analog input signal and outputs digital data. A statistical unit coupled to the ADC obtains samples of the output signal and transmits a control signal to the ADC to adjust the resolution of the ADC. The control signal is generated by the statistical unit based on a comparison of at least one performance indicator with a target performance level. The at least one performance indicator is calculated using the samples.

Dynamic control of ADC resolution

Systems and circuits for feedback control of an asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) are described. An example system includes the asynchronous SAR ADC. A timing detector circuit is coupled to the asynchronous SAR ADC to receive one or more internal signals from the asynchronous SAR ADC. The timing detector circuit outputs a timing detector signal representing an internal timing of the SAR ADC. The timing detector signal is generated based on the one or more internal signals. A regulator circuit is coupled to the timing detector circuit to receive the timing detector signal. The regulator circuit is also coupled to the asynchronous SAR ADC to output a feedback signal to the asynchronous SAR ADC. The feedback signal is generated based on the timing detector signal to control the internal timing of the SAR ADC to match a target timing.

Asynchronous SAR ADC with conversion speed control feedback loop

The present disclosure provides a system, circuit, and method for correcting clock skew in time-interleaved analog-to-digital converters. At least two clock signals are received along respective channels. A delay of a first channel, carrying a first clock signal, is accounted for by applying one or more first adjustment factors to the channels until an edge of the first clock signal is aligned with a transition point of a reference signal. The first clock signal is swapped to the second channel, and vice-versa. A value of the reference signal as sampled by the first clock signal is compared to values of the reference signal as sampled by the second clock signal to determine a skew of the second channel vis-&#xe0;-vis the first channel, and one or more second adjustment factors are applied to the second channel based on the determined skew of the second channel.

Skew detection and correction in time-interleaved analog-to-digital converters

A transadmittance amplifier stage is coupled to a transimpedance amplifier stage to form a continuous time linear equalizer. The transadmittance amplifier stage has first and second gain paths and is configured to input a first signal and output a second signal. The first gain path is configured to provide a DC gain recovery and a first high frequency gain to the first signal. The second gain path is configured to provide a second high frequency gain to the first signal. The second signal is generated by the transadmittance amplifier stage based on the gain recovery of the first signal and the high frequency gains of the first signal. The transimpedance amplifier stage is configured to input the second signal from the transadmittance amplifier stage and convert the second signal to an output voltage signal.

Dual path double zero continuous time linear equalizer

A front-end of a first differential circuit is DC-coupled to a second differential circuit. The front-end comprises a resistive element, a voltage sensor and a current adjustor. The resistive element has a resistivity between a first end that is DC-coupled to the second circuit and a second end that is DC-coupled to the first circuit and accepts a programmable current passing therethrough to impose a voltage across the element that varies in direction and amplitude according to the current value. The voltage sensor senses a difference between a DC voltage at the second end of the resistive element and a desired reference voltage of the first circuit. The current adjustor adjusts a direction and amplitude of the programmable current so that the voltage of the first circuit matches the desired reference voltage of the first circuit. The first circuit may be a receiver circuit and the second circuit may be a transmitter circuit. The front-end may further comprise a current canceller comprising a second resistive element connected at a first end to the output of the second circuit. The current canceller senses the programmable current and generates a current of equal amplitude through the second resistive element and away from the output of the second circuit. The current canceller may be implemented in digital or analog form and/or in differential or common-mode operation.

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Ottawa, Canada

Marc-Andre Lacroix