Freescale Semiconductor,inc.

Amkor Technology, Inc.

Amkor Technology Singapore Holding Pte. Ltd.

Marc Alan Mangrum

Kenneth R Burch

George R Leal

Robert Joseph Wenzel

Jie-Hua Zhao

Edward R Prack

David G Wontor

Brian D Sawyer

Byong Jin Kim

Gi Jeong Kim

Jae Min Bae

Seung Mo Kim

Young Ju Lee

Hyung Jun Cho

Jinbang Tang

Bora Baloglu

David Patten

Darrel R Frear

Adrian Arcedera

Jong-Kai Lin

Lawrence N Herr

Russell Shumway

Robert E Booth

William H Lytle

Victor Adrian Chiriac

Sergio A Ajuria

Anthony E Panczak

Ziep Tran

Melanie Etherton

Addi B Mistry

Tien Yu T Lee

Jesse Phou

Thinh Van Pham

Methods and system for flip chip alignment for substrate and leadframe applications are disclosed and may include placing a semiconductor die on bond fingers of a metal leadframe, wherein at least two of the bond fingers comprise one or more recessed self-alignment features. A reflow process may be performed on the semiconductor die and leadframe, thereby melting solder bumps on the semiconductor die such that a solder bump may be pulled into each of the recessed self-alignment features and aligning the solder bumps on the semiconductor die to the bond fingers. The recessed self-alignment features may be formed utilizing a chemical etch process or a stamping process. A surface of the recessed self-alignment features or the bond fingers of the metal leadframe may be roughened. A solder paste may be formed in the recessed self-alignment features prior to placing the semiconductor die on the bond fingers of the metal leadframe.

Flip chip self-alignment features for substrate and leadframe applications and method of manufacturing the flip chip self-alignment features

A method for forming packaged electronic device structure includes providing a conductive leadframe. The leadframe can include a die pad and a plurality of conductive leads. The method can include coupling an electronic device to the plurality of conductive leads. The method can include providing an antenna structure, which can include a conductive pillar structure and an elongated conductive beam structure. The method can include providing a package body encapsulating the electronic device, at least portions of each conductive lead, and at least portions of the die pad. In an example, the conductive pillar structure can extend from the first package body surface to the second package body surface, the elongated conductive beam structure can be disposed adjoining the first package body surface and can be electrically connected to the conductive pillar structure, and a portion of the elongated conductive beam structure can be exposed outside of the package body.

Packaged electronic device having integrated antenna and locking structure

A method for forming packaged electronic device structure includes providing a conductive leadframe. The leadframe can include a die pad with a first major surface and a second major surface opposite to the first major surface, and a plurality of conductive leads. The method can include coupling an electronic device to the plurality of conductive leads. The method can include providing an antenna structure, which can include a conductive pillar structure and an elongated conductive beam structure. The method can include providing a package body encapsulating the electronic device, at least portions of each conductive lead, and at least portions of the die pad. In an example, the conductive pillar structure can extend from the first package body surface to the second package body surface, the elongated conductive beam structure can be disposed adjoining the first package body surface and is electrically connected to the conductive pillar structure, and at least a portion of the elongated conductive beam structure is exposed outside of the package body.

Flip chip curved sidewall self-alignment features for substrate and method for manufacturing the self-alignment features

A packaged electronic device includes an integrated antenna as part of a conductive leadframe. The conductive leadframe includes a die paddle have an elongated conductive beam structure configured as a transmission line, and a ground plane structure disposed surrounding the die paddle. The ground plane includes a gap where the transmission line extends to an edge of the packaged electronic device. In one embodiment, selected leads within the leadframe are configured with conductive connective structures as ground pins, source pins, and/or wave guides. In an alternate embodiment, a portion of the integrated antenna is embedded and partially exposed within the body of the packaged electronic device.

Methods for an embedded vibration management system are disclosed and may include fabricating a semiconductor package that supports vibration management by forming an array of vibration absorbing structures, placing the array proximate to a leadframe comprising two-legged supported leads, placing a semiconductor device above the leadframe, and encapsulating the semiconductor device and the leadframe. Each vibration absorbing structure may comprise a mass element formed on a material with lower density than that of the mass element. The array may be placed on a top, a bottom, or both surfaces of the leadframe. Sections of the array may be placed symmetrically with respect to the semiconductor device. The vibration absorbing structures may be cubic in shape and may be enclosed in an encapsulating material. The two-legged supported leads may be formed by bending metal strips with holes. The vibration absorbing structures may be exposed to the exterior of the semiconductor package.

Embedded vibration management system having an array of vibration absorbing structures

Flip chip self-alignment features for substrate and leadframe applications

An electronic device structure includes a leadframe with a die pad and a lead. A semiconductor die is mounted adjacent to the die pad. A clip having a clip tail section is attached to the lead. The clip further has a clip top section attached to the clip tail section, and the clip top section is attached to a die top side of the semiconductor die with a conductive material. The clip further has an opening disposed to extend through the clip top section. In one embodiment, after a reflow step the conductive material forms a conductive fillet at least partially covering sidewall surfaces of the opening, and has a height within the opening with respect to a bottom surface of the clip top section. The opening and the conductive fillet provide an improved approach to monitoring coverage of the conductive material between the clip top section and the die top side of the semiconductor die.

Semiconductor package having inspection structure and related methods

Embedded vibration management system

A method of forming a packaged semiconductor device includes providing a conductive frame structure. The conductive frame structure includes a first frame having leadfingers configured for directly attaching to a semiconductor device, such as an integrated power semiconductor device that includes both power devices and logic type devices. The leadfingers are further configured to provide high current capacity and a high thermal dissipation capacity for the power device portion of the semiconductor device. In one embodiment, the conductive frame structure further includes a second frame joined to the first frame. The second frame includes a plurality of leads configured to electrically connect to low power device portions of the semiconductor device. A package body is formed to encapsulate the semiconductor device and at least portions of the leadfingers and leads.

Method of forming a semiconductor package with conductive interconnect frame and structure

An electronic component includes a leadframe and a first semiconductor die. The leadframe includes a leadframe top side, a leadframe bottom side opposite the leadframe top side, and a top notch at the leadframe top side. The top notch includes a top notch base located between the leadframe top side and the leadframe bottom side, and defining a notch length of the top notch, and can also include a top notch first sidewall extended, along the notch length, from the leadframe top side to the top notch base. The first semiconductor die can include a die top side a die bottom side opposite the die top side and mounted onto the leadframe top side, and a die perimeter. The top notch can be located outside the die perimeter. Other examples and related methods are also disclosed.

Semiconductor package with clip alignment notch

Growing community of inventors

Manchaca, TX, United States of America

Marc Alan Mangrum