Tensilica, Inc.

Rambus Inc.

Cadence Design Systems, Inc.

Marc Alan Evans

Pavlos Konas

Frederick Abbott Ware

Richard E Perego

Earl A Killian

Eileen Margaret Peters Long

Gulbin Ayse Ezer

John Barrett Andrews

Stephen Wei Chou

An automated system-on-chip (SOC) hardware and software cogeneration design flow allows an SOC designer, using a single source description for any platform-independent combination of reused or new IP blocks, to produce a configured hardware description language (HDL) description of the circuitry necessary to implement the SOC, while at the same time producing the development tools (e.g., compilers, assemblers, debuggers, simulator, software support libraries, reset sequences, etc.) used to generate the SOC software and the diagnostics environment used to verify the SOC.

Method for multiple processor system-on-a-chip hardware and software cogeneration

A method and apparatus provides a mask key that is used instead of mask data. In an embodiment of the present invention, a write mask key is generated by a memory controller and transferred to a memory device that uses the write mask key to determine whether to write a data value to a storage array. A plurality of decoders, an OR logic gate tree and a binary propagation tree is used to provide the write mask key that reduces latency while using the approximate same circuit area and allows for the use of standard software tools in an embodiment of the present invention. A plurality of logdecoders is coupled to a plurality of OR logic gates in the OR logic gate tree.

Method and apparatus for generating a write mask key

An MMU provides services at a cost more directly proportional to the needs of the system. According to one aspect, the MMU provides both address translation and sophisticated protection capabilities. Translation and protection are desirable when applications running on the processor are not completely debugged or trustable, for example. According to another aspect, a system for configuring the MMU design according to user specifications and system needs is provided. The MMU configurability aspects enable the system designer to configure MMUs having run-time programmability features that span the range from completely static to completely dynamic. In addition, the MMU can be configured to support variable page sizes, multiple protection and sharing rings, demand paging, and hardware TLB refill, for example.

Configurable memory management unit

A set-associative structure replacement algorithm is particularly beneficial for irregular set-associative structures which may be affected by different access patterns, and different associativities available to be replaced on any given access. According to certain aspects, methods and apparatuses implement a novel decay replacement algorithm that is particularly beneficial for irregular set-associative structures. An embodiment apparatus includes set-associative structures having decay information stored therein, as well as update/replacement logic to implement replacement algorithms for translation lookup buffers (TLBS) and caches that vary in the number of associativities; have unbalanced associativity sizes, e.g., associativities can have different numbers of indices; and can have varying replacement criteria. The implementation apparatuses and methods provide good performance, on the level of LRU, random and clock algorithms; and is efficient and scalable.

Set-associative cache memory having variable time decay rewriting algorithm

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San Jose, CA, United States of America

Marc Alan Evans